公开(公告)号：WO2019066998A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054682

申请日：2017-09-30

Applicant: INTEL CORPORATION ,  EID, Feras ,  SWAN, Johanna M. ,  LIFF, Shawna M.

Inventor： EID, Feras ,  SWAN, Johanna M. ,  LIFF, Shawna M.

IPC: H01L23/367 ,  H01L23/04 ,  H01L23/00 ,  H01L23/42 ,  H01L23/40

Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.

公开(公告)号：WO2019133018A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069156

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  DOGIAMIS, Georgios C. ,  OSTER, Sasha N. ,  KAMGAING, Telesphor ,  SHOEMAKER, Kenneth ,  EWY, Erich N. ,  ELSHERBINI, Adel A.

Inventor： DOGIAMIS, Georgios C. ,  OSTER, Sasha N. ,  KAMGAING, Telesphor ,  SHOEMAKER, Kenneth ,  EWY, Erich N. ,  ELSHERBINI, Adel A.

IPC: H01P3/16 ,  H01P3/13

Abstract: Embodiments include a waveguide bundle, a dielectric waveguide, and a vehicle. The waveguide bundle includes dielectric waveguides, where each dielectric waveguide has a dielectric core and a conductive coating around the dielectric core. The waveguide bundle also has a power delivery layer formed around the dielectric waveguides, and an insulating jacket enclosing the waveguide bundle. The waveguide bundle may also include the power deliver layer as a braided shield, where the braided shield provides at least one of a DC and an AC power line. The waveguide bundle may further have one of the dielectric waveguides provide a DC ground over their conductive coatings, where the AC power line does not use the braided shield as reference or ground. The waveguide bundle may include that the power delivery layer is separated from the dielectric waveguides by a braided shield, where the power delivery layer is a power delivery braided foil.

公开(公告)号：WO2019133017A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069155

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  STRONG, Veronica ,  ALEKSOV, Aleksandar ,  RAWLINGS, Brandon

Inventor： STRONG, Veronica ,  ALEKSOV, Aleksandar ,  RAWLINGS, Brandon

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/498 ,  H01L23/538 ,  H01L23/485 ,  H01L23/00

Abstract: A device package and method of forming the device package are described. The device package includes a dielectric on a conductive pad, a first via on a top surface of conductive pad, where the first via extends through dielectric, and a conductive trace on dielectric. The device package has a second via on dielectric, where the conductive trace connects to first and second vias, and the second via connects to an edge of conductive trace opposite from first via. The device package may have a seed on dielectric, where the seed electrically couples to conductive trace, a first seed on the top surface of conductive pad, where the first via is on first seed, and a second seed on a top surface of first via, the second seed on surfaces of second via, where the conductive trace is on second seed disposed on both first and second vias.

公开(公告)号：WO2019066994A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054678

申请日：2017-09-30

Applicant: INTEL CORPORATION ,  BRAUNISCH, Henning ,  EID, Feras ,  DOGIAMIS, Georgios C.

Inventor： BRAUNISCH, Henning ,  EID, Feras ,  DOGIAMIS, Georgios C.

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/12 ,  H01L23/40

Abstract: An inductor in a device package and a method of forming the inductor in the device package are described. The inductor includes a first conductive layer disposed on a substrate. The inductor also has one or more hybrid magnetic additively manufactured (HMAM) layers disposed over and around the first conductive layer to form one or more via openings over the first conductive layer. The inductor further includes one or more vias disposed into the one or more via openings, wherein the one or more vias are only disposed on the portions of the exposed first conductive layer. The inductor has a dielectric layer disposed over and around the one or more vias, the HMAM layers, and the substrate. The inductor also has a second conductive layer disposed over the one or more vias and the dielectric layer.

公开(公告)号：WO2019133020A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069158

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  DOGIAMIS, Georgios C. ,  OSTER, Sasha N. ,  ELSHERBINI, Adel A. ,  EWY, Erich N. ,  SWAN, Johanna M.

Inventor： DOGIAMIS, Georgios C. ,  OSTER, Sasha N. ,  ELSHERBINI, Adel A. ,  EWY, Erich N. ,  SWAN, Johanna M.

IPC: B60R16/023 ,  B60R16/03 ,  H04B1/08 ,  H04B1/3822 ,  H01P3/16

Abstract: Embodiments include a sensor node, an active sensor node, and a vehicle with a communication system that includes sensor nodes. The sensor node include a package substrate, a diplexer/combiner block on the package substrate, a transceiver communicatively coupled to the diplexer/combiner block, and a first mm-wave launcher coupled to the diplexer/combiner block. The sensor node may have a sensor communicatively coupled to the transceiver, the sensor is communicatively coupled to the transceiver by an electrical cable and located on the package substrate. The sensor node may include that the sensor operates at a frequency band for communicating with an electronic control unit (ECU) communicatively coupled to the sensor node. The sensor node may have a filter communicatively coupled to the diplexer/combiner block, the transceiver communicatively coupled to the filter, the filter substantially removes frequencies from RF signals other than the frequency band of the sensor.

公开(公告)号：WO2019133019A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069157

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  SANKMAN, Robert L. ,  GANESAN, Sanka

Inventor： SANKMAN, Robert L. ,  GANESAN, Sanka

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/00 ,  H01L23/485 ,  H01L23/28 ,  H01L23/42

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a base die disposed on an interposer. The semiconductor package also has a plurality of dies on top of one another to form a stack on the base die. Each die has a top surface and a bottom surface that is opposite from the top surface, and each die has one or more die contacts on at least one of the top surface and the bottom surface that are each electrically coupled to at least one die contact of the base die with one or more wire bonds. The semiconductor package includes a mold layer disposed over and around the plurality of dies, the base die, and the one or more wire bonds. The base die may have a first surface area that exceeds a second surface area of the plurality of stacked dies.

公开(公告)号：WO2019133016A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069154

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  ALEKSOV, Aleksandar ,  STRONG, Veronica ,  RAWLINGS, Brandon

Inventor： ALEKSOV, Aleksandar ,  STRONG, Veronica ,  RAWLINGS, Brandon

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/485 ,  H01L23/498 ,  H01L23/538

Abstract: A device package and a method of forming a device package are described. The device package includes a dielectric on a conductive pad, and a first via on a first seed on a top surface of the conductive pad. The device package further includes a conductive trace on the dielectric, and a second via on a second seed layer on the dielectric. The conductive trace connects to the first via and the second via, where the second via connects to an edge of the conductive trace opposite from the first via. The dielectric may include a photoimageable dielectric or a buildup film. The device package may also include a seed on the dielectric prior to the conductive trace on the dielectric, and a second dielectric on the dielectric, the conductive trace, and the first and second vias, where the second dielectric exposes a top surface of the second via.

公开(公告)号：WO2019133015A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069153

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  STRONG, Veronica ,  ALEKSOV, Aleksandar ,  RAWLINGS, Brandon

Inventor： STRONG, Veronica ,  ALEKSOV, Aleksandar ,  RAWLINGS, Brandon

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/485 ,  H01L23/00 ,  H01L23/498

Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

公开(公告)号：WO2019066992A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054676

申请日：2017-09-30

Applicant: INTEL CORPORATION ,  EID, Feras ,  SWAN, Johanna M. ,  CHAN ARGUEDAS, Sergio ,  BEATTY, John J.

Inventor： EID, Feras ,  SWAN, Johanna M. ,  CHAN ARGUEDAS, Sergio ,  BEATTY, John J.

IPC: H01L23/367 ,  H01L23/40

Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

公开(公告)号：WO2019066990A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054674

申请日：2017-09-30

Applicant: INTEL CORPORATION ,  EID, Feras

Inventor： EID, Feras

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/40

Abstract: A device package and a method of forming a device package are described. The device package includes a lid with one or more legs on an outer periphery of the lid, a top surface, and a bottom surface, where the lid is disposed on the substrate. The legs of the lid are attached to the substrate with a sealant. The device package also has one or more dies disposed on the substrate. The die(s) are below the bottom surface of the lid, where each of the dies has a top surface and a bottom surface. The device package further includes a retaining structure disposed between the bottom surface of the lid and the top surface of the die, where the retaining structure has one or more inner walls. The device package includes a thermal interface material disposed within the inner walls of the retaining structure and above the top surface of the die.