公开(公告)号：WO2016014731A1

公开(公告)日：2016-01-28

申请号：PCT/US2015/041636

申请日：2015-07-22

Applicant: APLUS FLASH TECHNOLOGY, INC.

Inventor： LEE, Peter, Wung

IPC: G11C8/14 ,  G11C11/40 ,  G11C16/04

CPC classification number: G11C11/5635 ,  G11C7/14 ,  G11C7/18 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/50 ,  G11C2029/5002

Abstract: A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch- based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common VSL-based Vt-compensation and VLBL compensations to mitigate high WL-WL and BL-BL coupling effects. Bias conditions in each string are provided to correctly sense highly-negative erase-verify voltage, multiple negative program-verify voltages and without VDS punch-through, breakdown and body-effect in both boundary and non-boundary WLs cells.

Abstract translation: 包含与分级全局/局部位线（GBL / LBL）相关联的多个串的YUKAI NAND阵列，每个串与一个LBL相关联，并且具有相邻的LBL作为专用本地源线（LSL），而没有公共源线连接所有字符串 。 每个LBL与通过插入每个串中的一对虚拟单元选择的奇数或偶数字符串进行交织关联，并且被用作具有完全BL屏蔽的一个片上PCACHE寄存器，而不浪费额外的硅面积以允许基于批次 多个并发的MLC全BL，全Vtn程序和替代WL程序，奇/偶读取和验证操作，具有提供单独和常见的基于VSL的Vt补偿和VLBL补偿的选项，以减轻高WL-WL和BL- BL耦合效应。 提供每个串中的偏置条件以正确检测边界和非边界WL单元中的高负值擦除验证电压，多个负编程验证电压以及VDS穿透，击穿和体效应。

公开(公告)号：WO2015039058A1

公开(公告)日：2015-03-19

申请号：PCT/US2014/055718

申请日：2014-09-16

Applicant: APLUS FLASH TECHNOLOGY, INC.

Inventor： LEE, Peter, Wung

IPC: G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459

Abstract: This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal 1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program- Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements.

Abstract translation: 本发明提供了可应用于2D和3D HiNAND2存储器阵列的2级BL分级NAND存储器架构和相关联的并行操作。 在块解码器和分段解码器中的新锁存器设计，每个2N位动态页面缓冲器（DPB），每个2N位动态页面缓冲器（DPB）形成一个共同的专用金属电源线，形成在对应的2N个断开LBL金属线路电容器中，用于编程和每个2N位段DPB形成 在相应的2N本地LBL金属1线读取电容器中提供用于执行多WL程序，读，擦除验证和编程验证的并行和流水线操作，分散块在相同或多个不同的NAND平面中具有大量增强的阵列 灵活性和多重性能改进。

公开(公告)号：WO2015013689A3

公开(公告)日：2015-01-29

申请号：PCT/US2014/048316

申请日：2014-07-25

Applicant: APLUS FLASH TECHNOLOGY, INC.

Inventor： LEE, Peter, Wung

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

Abstract: Several 2D and 3D HiNAND flash memory arrays with 1 -level or 2-level broken BL- hierarchical structures are provided for Multiple Whole- WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple l(top)-level broken metal2 GBLs plus optional lower-level broken metal 1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metalO power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple- WL and All-BL Program and Program- Verify operation with reduced program current for highest program yield superior P/E cycles.

公开(公告)号：WO2014210424A2

公开(公告)日：2014-12-31

申请号：PCT/US2014/044512

申请日：2014-06-27

Applicant: APLUS FLASH TECHNOLOGY, INC.

Inventor： Peter Wung Lee

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C8/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459

Abstract: This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1block bit lines (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program- Verify operations are replaced by multiple- WL and All-BL Read and Program- Verify operations executed with charge capacitance of SBLs being reduced to 1/10-1/20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed.

Abstract translation: 本发明公开了一种具有多级位线（BL）的HiNAND阵列方案，包括金属3全局位线（GBL），划分的金属2段位线（SBL）以及彼此平行布置的划分的金属块位线（BBL） 分别用于多个NAND串。 连接到GBL，SBL和BBL的相应串电容的底部的所有其他源极线或电源线与垂直于那些BL布置的金属线0相关联。 在HiNAND阵列方案下，传统的一WL读和编程验证操作由多次WL和全BL读取和程序验证操作替代，SBL的电荷电容降低到电容的1 / 10-1 / 20 的GBL以实现DRAM般的更快的操作，更少的操作压力和更低的功耗。 提出了所选择的WL和与乘法器和DRAM状电荷共享锁存放大器相关联的剩余未选择的WL的优选的一组编程偏置电压。

公开(公告)号：WO2013075067A1

公开(公告)日：2013-05-23

申请号：PCT/US2012/065734

申请日：2012-11-18

Applicant: APLUS FLASH TECHNOLOGY, INC. ,  LEE, Peter, W. ,  TSAO, Hsing-Ya

Inventor： LEE, Peter, W. ,  TSAO, Hsing-Ya

IPC: G11C5/14

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16

Abstract: A low-current FN channel for Erase, Program, Program-Inhibit and Read operations is disclosed for any non-volatile memory using FN-tunneling scheme for program and erase operation, regardless NAND, NOR, and EEPROM and regardless PMOS or NMOS non-volatile cell type. As a result, all above NMV memories can use the disclosed LV, compact PGM buffer to replace the traditional HV PGM buffer for saving in the silicon area and power consumption. The page buffer is used to store new loaded data for new writing and to convert the stored data into the required BL HV voltage for either Erase or Program operations according to the stored data. In addition, the simpler on-chip State-machine design can be achieved with the superior quality of NVMs of this disclosure.

Abstract translation: 公开了用于擦除，编程，程序禁止和读操作的低电流FN通道，用于使用用于编程和擦除操作的FN隧道方案的任何非易失性存储器，无论NAND，NOR和EEPROM，以及不管PMOS或NMOS非 - 挥发性细胞类型。 因此，所有上述NMV存储器都可以使用所公开的LV，紧凑型PGM缓冲器来替代传统的HV PGM缓冲器，以节省硅面积和功耗。 页面缓冲区用于存储用于新写入的新加载数据，并将存储的数据转换为所需的BL HV电压，以根据存储的数据进行擦除或编程操作。 此外，可以通过本公开的NVM的优越品质来实现更简单的片上状态机设计。

公开(公告)号：WO2012103075A1

公开(公告)日：2012-08-02

申请号：PCT/US2012/022340

申请日：2012-01-24

Applicant: APLUS FLASH TECHNOLOGY, INC. ,  LEE, Peter, W. ,  HSU, Fu-Chang

Inventor： LEE, Peter, W. ,  HSU, Fu-Chang

IPC: G11C11/34

CPC classification number: G06F12/1425 ,  G06F21/31 ,  G06F21/79 ,  G06F2212/2022 ,  G11C16/0458 ,  G11C16/22

Abstract: A memory access apparatus that controls access to at least one memory array has an array of programmable comparison cells that retain a programmed pass code and compare it with an access pass code. When there is a match between the access pass code and the programmed pass code, the memory access apparatus generates a match signal for allowing access to the at least one memory array. If there is no match, the data within the at least one memory array may be corrupted or destroyed. Each nonvolatile comparison cell has a pair of series connected charge retaining transistors. The programmed pass code is stored in the charge retaining transistors. Primary and complementary query pass codes are applied to the charge retaining transistors and are logically compared with the stored pass code and based on the programmed threshold voltage levels determine if the query pass code is correct.

Abstract translation: 控制对至少一个存储器阵列的访问的存储器访问装置具有保持编程的密码并将其与访问密码进行比较的可编程比较单元的阵列。 当访问密码与编程密码之间存在匹配时，存储器访问设备产生用于允许访问至少一个存储器阵列的匹配信号。 如果没有匹配，则至少一个存储器阵列内的数据可能被破坏或破坏。 每个非易失性比较单元具有一对串联连接的电荷保持晶体管。 编程的密码存储在电荷保持晶体管中。 主要和互补的查询密码被应用于电荷保持晶体管，并且与存储的密码进行逻辑比较，并且基于编程的阈值电压电平确定查询密码是否正确。

公开(公告)号：WO2012036751A2

公开(公告)日：2012-03-22

申请号：PCT/US2011/001609

申请日：2011-09-19

Applicant: APLUS FLASH TECHNOLOGY, INC. ,  LEE, Peter, W. ,  HSU, Fu-Chang

Inventor： LEE, Peter, W. ,  HSU, Fu-Chang

IPC: G06F12/00 ,  H05K3/00

CPC classification number: G06F12/0638 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C11/005 ,  G11C16/32 ,  G11C2216/30 ,  Y02D10/13 ,  Y10T29/49124

Abstract: A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as l 2 C, SPI, SDI and SQI in one memory chip. The memory chip features write- while-write and read-while-write operations as well as read-while-transfer and write- while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

Abstract translation: 半导体芯片在一个存储器芯片中包含四种不同的存储器类型，即EEPROM，NAND闪存，NOR闪存和SRAM以及多个主要的串行/并行接口，例如l2C，SPI，SDI和SQI。 内存芯片具有写时同时写入和读写操作以及读写同时传输和写时传输操作。 存储器芯片提供八个引脚，其中两个用于供电，最多四个引脚没有连接用于特定接口，并且使用新颖的统一的非易失性存储器设计，允许集成在一起的上述存储器类型集成在同一半导体存储器芯片 。

公开(公告)号：WO2012033533A1

公开(公告)日：2012-03-15

申请号：PCT/US2011/001561

申请日：2011-09-09

Applicant: APLUS FLASH TECHNOLOGY, INC. ,  LEE, Peter, W. ,  HSU, Fu-chang

Inventor： LEE, Peter, W. ,  HSU, Fu-chang

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  G11C11/005 ,  G11C16/12 ,  G11C16/3436

Abstract: Disclosed is a low-cost hybrid storage solution that allows Code like sectoralterable NOR and Data like block-alterable NAND and byte-alterable EEPROM being integrated on a same die. The disclosed combo NVM design of the present invention is a truly Data-oriented NVM design that allows 2T-EEPROM to integrate both O ST-NAND and 1 T -NOR without sacrificing any EEPROM's byte-write performance in the same die. The invention provides several new embodiment sets of preferable bias conditions of Program, Program-Inhibit, Erase and Erase-lnhibit for operating bit-write, byte-write, sector-write and page-write for several preferable Flotox-based EEPROM, NOR and NAND or combo NVM arrays that include types of shared SL, 8-pair BLs and SLS, with or without GBL, normally Erased Vt and Programmed Vt, or the reversed Erased-Vt or Programmed-Vt, etc. Further disclosed is a flexible X-decoder design to allow the flexible selection of pages to be erased to save erase time.

Abstract translation: 公开了一种低成本混合存储解决方案，其允许代码像扇区可逆NOR和数据像块可更改的NAND和字节可变EEPROM被集成在同一个芯片上。 本发明的公开的组合NVM设计是真正的面向数据的NVM设计，允许2T-EEPROM将O ST-NAND和1-N -NOR集成在一起，而不牺牲同一芯片中的任何EEPROM的字节写入性能。 本发明提供了若干优选的基于Flotox的EEPROM，NOR和编程的程序，程序抑制，擦除和擦除的几种新的实施例集合，用于操作位写入，字节写入，扇区写入和寻呼 NAND或组合NVM阵列，包括具有或不具有GBL的共享SL，8对BL和SLS的类型，通常为已擦除Vt和编程Vt，或反向擦除Vt或编程Vt等。还公开了一种灵活的X -decoder设计允许页面的灵活选择被擦除以节省擦除时间。

公开(公告)号：WO2009151581A1

公开(公告)日：2009-12-17

申请号：PCT/US2009/003472

申请日：2009-06-09

Applicant: APLUS FLASH TECHNOLOGY, INC. ,  LEE, Peter, Wung ,  HSU, Fu-chang ,  TSAO, Hsing-ya

Inventor： LEE, Peter, Wung ,  HSU, Fu-chang ,  TSAO, Hsing-ya

IPC: G11C7/22

CPC classification number: G11C16/0416 ,  G11C11/5621 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3436 ,  G11C2211/5621

Abstract: An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.

Abstract translation: 用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障 。 该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

公开(公告)号：WO2007064988A2

公开(公告)日：2007-06-07

申请号：PCT/US2006/046209

申请日：2006-12-01

Applicant: APLUS FLASH TECHNOLOGY, INC. ,  MA, Han-rei ,  HSU, Fu-Chang ,  LEE, Peter, W. ,  HONG, Xiang

Inventor： MA, Han-rei ,  HSU, Fu-Chang ,  LEE, Peter, W. ,  HONG, Xiang

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

Abstract: The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present invention also include a high voltage PMOS placed on top of a deep N- well and NMOS placed above a triple P-well inside the deep N- well in the peripheral area to pass both positive and negative high voltage of around +20V and -20V to the cell area. In one embodiment, the cell array, source lines and bit lines are all placed on top of the P-substrate without a deep N-well or Triple P- well. In other embodiments, the cell array, source lines and bit lines are placed on top of the deep N-well and triple P-well.

Abstract translation: 本发明的器件包括形成在半导体衬底的预定区域并彼此平行延伸的多个隔离层。 本发明的器件还包括放置在深N阱的顶部的高电压PMOS和位于外围区域的深N阱内的三重P阱上方的NMOS，以通过周围的正和负高电压 + 20V和-20V到细胞区域。 在一个实施例中，单元阵列，源极线和位线都被放置在P衬底的顶部上，而没有深N阱或三重P阱。 在其他实施例中，将单元阵列，源极线和位线放置在深N阱和三重P阱的顶部。