公开(公告)号：WO2013095545A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066985

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  MELLINGER, Todd W. ,  GRIFFITH, Michael E. ,  BALAMURUGAN, Ganesh ,  THOMAS, Thomas P.

Inventor： MELLINGER, Todd W. ,  GRIFFITH, Michael E. ,  BALAMURUGAN, Ganesh ,  THOMAS, Thomas P.

IPC: G06F1/00 ,  G06F13/14

CPC classification number: H02H9/046 ,  G06F1/16 ,  G06F1/1613 ,  H01L27/0255 ,  H03K19/00361

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Abstract translation: 一个封装接口。 第一组第一组单端发射机电路。 第二组芯片上的第一组单端接收器电路。 接收器电路具有包括反相器和电阻反馈元件的终端电路。 多条导线耦合第一组发射机电路和第一组接收机电路。 多条导线的长度相匹配。

公开(公告)号：WO2013095567A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067019

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  MELLINGER, Todd W. ,  GRIFFITH, Michael E. ,  BALAMURUGAN, Ganesh ,  THOMAS, Thomas P. ,  KUMAR, Rajesh

Inventor： MELLINGER, Todd W. ,  GRIFFITH, Michael E. ,  BALAMURUGAN, Ganesh ,  THOMAS, Thomas P. ,  KUMAR, Rajesh

IPC: G06F1/00 ,  G06F13/14

CPC classification number: G06F13/4086 ,  G06F13/14 ,  G06F13/36 ,  Y02D10/14 ,  Y02D10/151

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Abstract translation: 一个封装接口。 第一组第一组单端发射机电路。 第二组芯片上的第一组单端接收器电路。 接收器电路具有包括反相器和电阻反馈元件的终端电路。 多条导线耦合第一组发射机电路和第一组接收机电路。 多条导线的长度相匹配。

公开(公告)号：WO2005027446A1

公开(公告)日：2005-03-24

申请号：PCT/US2004/029175

申请日：2004-09-08

Applicant: INTEL CORPORATION ,  BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

Inventor： BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

IPC: H04L25/03

CPC classification number: H03H21/0043 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L25/03038 ,  H04L25/03885 ,  H04L2025/03477 ,  H04L2025/03617

Abstract: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: (I), where (II) is the filter vector representing the filter taps of the FIR filter, (III) is the data vector representing present and past samples of the received data x (t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, µ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K .

Abstract translation: 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：（I），其中（II）是表示 FIR滤波器的滤波器抽头（III）是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z（t）是 FIR滤波器，μ确定适配的存储器或窗口大小，K是考虑通信信道，接收机和均衡器的实际限制的比例因子。 此外，提供了用于校准比例因子K的过程和电路结构。