公开(公告)号：WO2013085495A1

公开(公告)日：2013-06-13

申请号：PCT/US2011/063566

申请日：2011-12-06

Applicant: INTEL CORPORATION ,  JAUSSI, James E. ,  MOONEY, Stephen R. ,  HECK, Howard L. ,  PEDERSON, Bruce E

Inventor： JAUSSI, James E. ,  MOONEY, Stephen R. ,  HECK, Howard L. ,  PEDERSON, Bruce E

IPC: H01R12/71 ,  H01R13/646

CPC classification number: H03K19/0008 ,  H01R12/722 ,  H01R12/727 ,  H01R13/6658 ,  H01R24/60 ,  H01R25/006 ,  H03K19/0175

Abstract: Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.

Abstract translation: 公开了具有多个托架并且包括围绕多对基板的壳体的可伸缩输入/输出接口。 一对基板中的第一基板可以具有第一接触表面，并且该对基板的第二基板可以具有与第一接触表面相对的第二接触表面，其中每个基板具有连接边缘。 至少一个集成缓冲器可以耦合到每个衬底的第一侧或第二侧。 可以将多排触点耦合到一对基板的每个基板的相对表面，其中每排触点可以基本上平行于连接边缘堆叠。 每个连接边缘也可以耦合到单独的集成缓冲器。

公开(公告)号：WO2013058730A1

公开(公告)日：2013-04-25

申请号：PCT/US2011/056581

申请日：2011-10-17

Applicant: INTEL CORPORATION ,  MOONEY, Stephen R. ,  HECK, Howard L ,  JAUSSI, James E. ,  HADY, Frank T. ,  CASPER, Bryan K.

Inventor： MOONEY, Stephen R. ,  HECK, Howard L ,  JAUSSI, James E. ,  HADY, Frank T. ,  CASPER, Bryan K.

IPC: G06F13/14 ,  G06F1/00

CPC classification number: G06F13/385 ,  G06F1/266 ,  H01H9/54 ,  H01R13/6658 ,  Y10T307/74

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.

Abstract translation: 互连设备的系统和方法可以包括具有电压调节器，一个或多个信令电路，第一组触点，连接到一个或多个信号电路的第二组触点和逻辑电路的输入/输出（IO）连接器组件 接收配置命令。 如果配置命令对应于第一协议，逻辑还可以将第一组触点连接到电压调节器。 如果配置命令对应于第二协议，另一方面，逻辑可以将第一组联系人连接到一个或多个信令电路。

公开(公告)号：WO2013058729A1

公开(公告)日：2013-04-25

申请号：PCT/US2011/056574

申请日：2011-10-17

Applicant: INTEL CORPORATION ,  JAUSSI, James E. ,  MOONEY, Stephen R. ,  HECK, Howard L ,  CASPER, Bryan K. ,  HADY, Frank T.

Inventor： JAUSSI, James E. ,  MOONEY, Stephen R. ,  HECK, Howard L ,  CASPER, Bryan K. ,  HADY, Frank T.

IPC: G06F13/14 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/266 ,  G06F1/3203

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.

Abstract translation: 互连设备的系统和方法可以包括具有集成稳压器的缓冲器的输入/输出（IO）连接器。 集成电压调节器可以包括第一电源输出和第二电源输出，其中IO连接器包括耦合到第一电源输出的IO电源触点。 IO连接器还可以包括耦合到第二电源输出的逻辑电源触点。 在一个示例中，主机设备可以向缓冲器发布功率管理命令，以便与第一电源输出独立地缩放第二电源输出。

公开(公告)号：WO2005027446A1

公开(公告)日：2005-03-24

申请号：PCT/US2004/029175

申请日：2004-09-08

Applicant: INTEL CORPORATION ,  BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

Inventor： BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

IPC: H04L25/03

CPC classification number: H03H21/0043 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L25/03038 ,  H04L25/03885 ,  H04L2025/03477 ,  H04L2025/03617

Abstract: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: (I), where (II) is the filter vector representing the filter taps of the FIR filter, (III) is the data vector representing present and past samples of the received data x (t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, µ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K .

Abstract translation: 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：（I），其中（II）是表示 FIR滤波器的滤波器抽头（III）是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z（t）是 FIR滤波器，μ确定适配的存储器或窗口大小，K是考虑通信信道，接收机和均衡器的实际限制的比例因子。 此外，提供了用于校准比例因子K的过程和电路结构。

公开(公告)号：WO2005109148A1

公开(公告)日：2005-11-17

申请号：PCT/US2005/012075

申请日：2005-04-08

Applicant: INTEL CORPORATION ,  KENNEDY, Joseph ,  MOONEY, Stephen

Inventor： KENNEDY, Joseph ,  MOONEY, Stephen

IPC: G06F1/10

CPC classification number: H03L7/0812

Abstract: A chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal.

Abstract translation: 一个芯片包括一个芯片接口，用于接受来自芯片外部的延迟控制信号。 芯片还包括可控延迟线，以响应于延迟控制信号来延迟输入信号，以提供具有与输入信号的特定相位关系的输出信号。

公开(公告)号：WO2005066968A1

公开(公告)日：2005-07-21

申请号：PCT/US2004/043496

申请日：2004-12-22

Applicant: INTEL CORPORATION ,  ELLIS, Robert, M. ,  MOONEY, Stephen, R. ,  KENNEDY, Joseph, T.

Inventor： ELLIS, Robert, M. ,  MOONEY, Stephen, R. ,  KENNEDY, Joseph, T.

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C5/14 ,  G11C11/4074 ,  G11C2207/104 ,  G11C2211/4067

Abstract: A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.

Abstract translation: 具有被提供有比提供给存储器逻辑的单独功率分开的更高电压功率的存储单元的存储器件，以及需要从逻辑中的至少一些去除功率的较低功率状态，使得刷新操作以保持存储器单元的内容 继续发生，但至少有一些到存储器件的接口掉电以降低功耗。

公开(公告)号：WO2013070239A1

公开(公告)日：2013-05-16

申请号：PCT/US2011/060376

申请日：2011-11-11

Applicant: INTEL CORPORATION ,  MOONEY, Stephen, R. ,  HECK, Howard, L ,  JAUSSI, James, E. ,  CASPER, Bryan, K. ,  CHOUDHURY, Debabani ,  HADY, Frank, T.

Inventor： MOONEY, Stephen, R. ,  HECK, Howard, L ,  JAUSSI, James, E. ,  CASPER, Bryan, K. ,  CHOUDHURY, Debabani ,  HADY, Frank, T.

IPC: G06F1/00 ,  H04W92/02 ,  H04L29/10

CPC classification number: H04B1/40 ,  G06F13/4068 ,  G06F2213/0042

Abstract: Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts.

Abstract translation: 互连设备的系统和方法可以包括具有基板，一组输入/输出（IO）触点，天线结构和收发器逻辑的连接器组件。 在一个示例中，收发器逻辑可以处理与天线结构相关联的一个或多个IO信号并且处理与该组IO触点相关联的一个或多个IO信号。

公开(公告)号：WO2013048508A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054452

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  JAUSSI, James, E. ,  MOONEY, Stephen, R. ,  CASPER, Bryan, K. ,  HECK, Howard, L.

Inventor： JAUSSI, James, E. ,  MOONEY, Stephen, R. ,  CASPER, Bryan, K. ,  HECK, Howard, L.

IPC: G06F13/14 ,  G06F13/38

CPC classification number: H04L41/0896 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods of interconnecting devices may include an input/output (10) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device- side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device- side data lanes based on the bandwidth configuration command.

Abstract translation: 互连设备的系统和方法可以包括具有一个或多个设备侧数据通道的输入/输出（10）接口和用于接收带宽配置命令的收发机逻辑。 收发器逻辑还可以基于带宽配置命令来配置一个或多个设备侧数据通道的发送带宽。 此外，收发器逻辑可以基于带宽配置命令来配置一个或多个设备侧数据通道的接收带宽。

公开(公告)号：WO2012078632A1

公开(公告)日：2012-06-14

申请号：PCT/US2011/063531

申请日：2011-12-06

Applicant: LOCKERZ, INC. ,  DESTEIN, Bill ,  BORTNIK, Michal ,  ZHU, Qinchao ,  MOONEY, Stephen

Inventor： DESTEIN, Bill ,  BORTNIK, Michal ,  ZHU, Qinchao ,  MOONEY, Stephen

IPC: G06Q30/00

CPC classification number: G06Q30/0276

Abstract: A system and method for creating shareable Internet-based advertisements includes administration console receiving data for Internet-based advertisement from a client, configuring an overlay to provide on top of the Internet-based advertisement. A database operatively connected to the administration console stores data and code related to overlay and advertisement. A share tag is applied to the advertisement, the share tag including a script reference pointing to the stored data and code stored in database. A share tag server retrieves the stored data and code and displays the overlay on the advertisement as an expanded share tag, upon activation of the share tag of the advertisement published on a content website. Upon activation of a share feature on the expanded share tag, the share tag server provides, to a desired social media network server, the stored data needed to display the advertisement on the user's social media network page.

Abstract translation: 用于创建可共享的基于因特网的广告的系统和方法包括管理控制台从客户端接收基于因特网的广告的数据，配置覆盖以在基于因特网的广告之上提供。 可操作地连接到管理控制台的数据库存储与覆盖和广告相关的数据和代码。 共享标签被应用于广告，共享标签包括指向存储的数据的脚本引用和存储在数据库中的代码。 共享标签服务器在激活内容网站上发布的广告的共享标签时，检索存储的数据和代码，并将广告上的叠加层显示为扩展的共享标签。 在激活扩展的共享标签上的共享功能之后，共享标签服务器向期望的社交媒体网络服务器提供在用户的社交媒体网络页面上显示广告所需的所存储的数据。

公开(公告)号：WO2007089885A3

公开(公告)日：2007-11-15

申请号：PCT/US2007002722

申请日：2007-01-30

Applicant: INTEL CORP ,  BANERJEE GAURAB ,  MOONEY STEPHEN

Inventor： BANERJEE GAURAB ,  MOONEY STEPHEN

IPC: H05K1/02 ,  H01L23/66 ,  H01P5/02 ,  H05K1/14

CPC classification number: H05K1/025 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P5/02 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09736 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A passive impedance equalization network (250,255,260,265) for high speed serial links is described. The impedance equalization network may include at least one stepped impedance transformer near points of impedance discontinuities (205,225,210,230). The impedance discontinuities may be at an interface connection between two circuit boards. The impedance discontinuities on a circuit board may be at a die-package interface and/or a package-board interface. The stepped impedance transformer may be formed in a package trace, a board trace or both. Forming the stepped impedance transformers in the traces requires no modification to existing package/board design methodology or technology. The stepped impedance transformers can provide impedance matching over a range of frequencies. To account for modeling errors in the design of the stepped impedance transformers integrated circuits transmitting data over the serial link may include active circuitry to select an output/input impedance for transmitters/receivers. Other embodiments are otherwise disclosed herein.

Abstract translation: 描述了用于高速串行链路的无源阻抗均衡网络（250,255,260,265）。 阻抗均衡网络可以包括在阻抗不连续点附近的至少一个阶梯式阻抗变压器（205,225,210,230）。 阻抗不连续性可能在两个电路板之间的接口连接处。 电路板上的阻抗不连续性可能在管芯封装接口和/或封装板接口处。 阶梯式阻抗变压器可以形成为封装迹线，板迹线或两者。 在走线中形成阶梯式阻抗变压器不需要修改现有的封装/电路板设计方法或技术。 阶梯式阻抗变压器可以在一定频率范围内提供阻抗匹配。 为了解决在阶梯式阻抗变压器的设计中的建模误差，通过串行链路传输数据的集成电路可能包括用于选择发射机/接收机的输出/输入阻抗的有源电路。 其他实施例在此另外公开。