公开(公告)号：WO2011081846A2

公开(公告)日：2011-07-07

申请号：PCT/US2010059853

申请日：2010-12-10

Applicant: INTEL CORP ,  DUNNING DAVE ,  CASPER BRYAN ,  MOONEY RANDY ,  MANSURI MOZHGAN ,  JAUSSI JAMES E

Inventor： DUNNING DAVE ,  CASPER BRYAN ,  MOONEY RANDY ,  MANSURI MOZHGAN ,  JAUSSI JAMES E

IPC: G11C5/02

CPC classification number: G06F11/1076 ,  G11C5/02 ,  G11C29/12 ,  H01L2224/16145 ,  H03M13/15 ,  H03M13/152

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract translation: 本发明的实施例一般涉及用于混合存储器的系统，方法和装置。 在一个实施例中，混合存储器可以包括封装衬底。 混合存储器还可以包括附接到封装衬底的第一侧的混合存储器缓冲芯片。 高速输入/输出（HSIO）逻辑支持与处理器的HSIO接口。 混合存储器还包括在HSIO接口上支持分组处理协议的分组处理逻辑。 此外，混合存储器还具有垂直堆叠在混合存储器缓冲器上的一个或多个存储器片。

公开(公告)号：WO2018119153A2

公开(公告)日：2018-06-28

申请号：PCT/US2017/067739

申请日：2017-12-20

Applicant: INTEL CORPORATION ,  INTEL IP CORPORATION ,  ALPMAN, Erkan ,  AMADJIKPE, Arnaud Lucres ,  OSAF, Omer ,  AZADET, Kameran ,  BANIN, Rotem ,  BARYAKH, Miroslav ,  BAZOV, Anat ,  BRENNA, Stefano ,  CASPER, Bryan K. ,  CHAKRABARTI, Anandaroop ,  CHANCE, Gregory ,  CHOUDHURY, Debabani ,  COHEN, Emanuel ,  DA SILVA, Claudio ,  DALMIA, Sidharth ,  DANESHGAR ASL, Saeid ,  DASGUPTA, Kaushik ,  DATTA, Kunal ,  DAVIS, Brandon ,  DEGANI, Ofir ,  FAHIM, Amr M. ,  FREIMAN, Amit ,  GENOSSAR, Michael ,  GERSON, Eran ,  GOLDBERGER, Eyal ,  GORDON, Eshel ,  GORDON, Meir ,  HAGN, Josef ,  KANG, Shinwon ,  KAO, Te Yu ,  KOGAN, Noam ,  KOMULAINEN, Mikko S. ,  KUSHNIR, Igal Yehuda ,  LAHTI, Saku ,  LAMPINEN, Mikko M. ,  LANDSBERG, Naftali ,  LEE, Wook Bong ,  LEVINGER, Run ,  MOLINA, Albert ,  MONTOYA MORENO, Resti ,  MUSAH, Tawfiq ,  NAREVSKY, Nathan G. ,  NIKOPOUR, Hosein ,  ORHAN, Oner ,  PALASKAS, Georgios ,  PELLERANO, Stefano ,  PONGRATZ, Ron ,  RAVI, Ashoke ,  RAVID, Shmuel ,  SAGAZIO, Peter Andrew ,  SASOGLU, Eren ,  SHAKEDD, Lior ,  SHOR, Gadi ,  SINGH, Baljit ,  SOFFER, Menashe ,  SOVER, Ra'anan ,  TALWAR, Shilpa ,  TANZI, Nebil ,  TEPLITSKY, Moshe ,  THAKKAR, Chintan S. ,  THAKUR, Jayprakash ,  TSARFATI, Avi ,  TSFATI, Yossi ,  VERHELST, Marian ,  WEISMAN, Nir ,  YAMADA, Shuhei ,  YEPES, Ana M. ,  KITCHIN, Duncan

Inventor： ALPMAN, Erkan ,  AMADJIKPE, Arnaud Lucres ,  OSAF, Omer ,  AZADET, Kameran ,  BANIN, Rotem ,  BARYAKH, Miroslav ,  BAZOV, Anat ,  BRENNA, Stefano ,  CASPER, Bryan K. ,  CHAKRABARTI, Anandaroop ,  CHANCE, Gregory ,  CHOUDHURY, Debabani ,  COHEN, Emanuel ,  DA SILVA, Claudio ,  DALMIA, Sidharth ,  DANESHGAR ASL, Saeid ,  DASGUPTA, Kaushik ,  DATTA, Kunal ,  DAVIS, Brandon ,  DEGANI, Ofir ,  FAHIM, Amr M. ,  FREIMAN, Amit ,  GENOSSAR, Michael ,  GERSON, Eran ,  GOLDBERGER, Eyal ,  GORDON, Eshel ,  GORDON, Meir ,  HAGN, Josef ,  KANG, Shinwon ,  KAO, Te Yu ,  KOGAN, Noam ,  KOMULAINEN, Mikko S. ,  KUSHNIR, Igal Yehuda ,  LAHTI, Saku ,  LAMPINEN, Mikko M. ,  LANDSBERG, Naftali ,  LEE, Wook Bong ,  LEVINGER, Run ,  MOLINA, Albert ,  MONTOYA MORENO, Resti ,  MUSAH, Tawfiq ,  NAREVSKY, Nathan G. ,  NIKOPOUR, Hosein ,  ORHAN, Oner ,  PALASKAS, Georgios ,  PELLERANO, Stefano ,  PONGRATZ, Ron ,  RAVI, Ashoke ,  RAVID, Shmuel ,  SAGAZIO, Peter Andrew ,  SASOGLU, Eren ,  SHAKEDD, Lior ,  SHOR, Gadi ,  SINGH, Baljit ,  SOFFER, Menashe ,  SOVER, Ra'anan ,  TALWAR, Shilpa ,  TANZI, Nebil ,  TEPLITSKY, Moshe ,  THAKKAR, Chintan S. ,  THAKUR, Jayprakash ,  TSARFATI, Avi ,  TSFATI, Yossi ,  VERHELST, Marian ,  WEISMAN, Nir ,  YAMADA, Shuhei ,  YEPES, Ana M. ,  KITCHIN, Duncan

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：WO2013058730A1

公开(公告)日：2013-04-25

申请号：PCT/US2011/056581

申请日：2011-10-17

Applicant: INTEL CORPORATION ,  MOONEY, Stephen R. ,  HECK, Howard L ,  JAUSSI, James E. ,  HADY, Frank T. ,  CASPER, Bryan K.

Inventor： MOONEY, Stephen R. ,  HECK, Howard L ,  JAUSSI, James E. ,  HADY, Frank T. ,  CASPER, Bryan K.

IPC: G06F13/14 ,  G06F1/00

CPC classification number: G06F13/385 ,  G06F1/266 ,  H01H9/54 ,  H01R13/6658 ,  Y10T307/74

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.

Abstract translation: 互连设备的系统和方法可以包括具有电压调节器，一个或多个信令电路，第一组触点，连接到一个或多个信号电路的第二组触点和逻辑电路的输入/输出（IO）连接器组件 接收配置命令。 如果配置命令对应于第一协议，逻辑还可以将第一组触点连接到电压调节器。 如果配置命令对应于第二协议，另一方面，逻辑可以将第一组联系人连接到一个或多个信令电路。

公开(公告)号：WO2013058729A1

公开(公告)日：2013-04-25

申请号：PCT/US2011/056574

申请日：2011-10-17

Applicant: INTEL CORPORATION ,  JAUSSI, James E. ,  MOONEY, Stephen R. ,  HECK, Howard L ,  CASPER, Bryan K. ,  HADY, Frank T.

Inventor： JAUSSI, James E. ,  MOONEY, Stephen R. ,  HECK, Howard L ,  CASPER, Bryan K. ,  HADY, Frank T.

IPC: G06F13/14 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/266 ,  G06F1/3203

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.

Abstract translation: 互连设备的系统和方法可以包括具有集成稳压器的缓冲器的输入/输出（IO）连接器。 集成电压调节器可以包括第一电源输出和第二电源输出，其中IO连接器包括耦合到第一电源输出的IO电源触点。 IO连接器还可以包括耦合到第二电源输出的逻辑电源触点。 在一个示例中，主机设备可以向缓冲器发布功率管理命令，以便与第一电源输出独立地缩放第二电源输出。

公开(公告)号：WO2005027446A1

公开(公告)日：2005-03-24

申请号：PCT/US2004/029175

申请日：2004-09-08

Applicant: INTEL CORPORATION ,  BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

Inventor： BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

IPC: H04L25/03

CPC classification number: H03H21/0043 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L25/03038 ,  H04L25/03885 ,  H04L2025/03477 ,  H04L2025/03617

Abstract: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: (I), where (II) is the filter vector representing the filter taps of the FIR filter, (III) is the data vector representing present and past samples of the received data x (t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, µ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K .

Abstract translation: 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：（I），其中（II）是表示 FIR滤波器的滤波器抽头（III）是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z（t）是 FIR滤波器，μ确定适配的存储器或窗口大小，K是考虑通信信道，接收机和均衡器的实际限制的比例因子。 此外，提供了用于校准比例因子K的过程和电路结构。

公开(公告)号：WO2013147839A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031408

申请日：2012-03-30

Applicant: INTEL CORPORATION ,  O'MAHONY, Frank ,  CASPER, Bryan K. ,  MANSURI, Mozhgan

Inventor： O'MAHONY, Frank ,  CASPER, Bryan K. ,  MANSURI, Mozhgan

IPC: G01R23/175 ,  H03K5/13 ,  H03L7/081

CPC classification number: G01R31/31725 ,  G01R25/08 ,  G01R31/31726 ,  G04F10/005 ,  H03K2005/00052

Abstract: An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.

Abstract translation: 在集成电路（IC）芯片上构造的全数字延迟测量电路（DMC）表征了也在IC芯片上构造的诸如全相位旋转内插器的时钟电路。 片上全数字DMC产生与两个时钟之间的相对延迟成比例的数字输出值，归一化为两个时钟的时钟周期。

公开(公告)号：WO2013062565A1

公开(公告)日：2013-05-02

申请号：PCT/US2011/058194

申请日：2011-10-28

Applicant: INTEL CORPORATION ,  MOONEY, Stephen R. ,  HECK, Howard L ,  JAUSSI, James E. ,  CASPER, Bryan K.

Inventor： MOONEY, Stephen R. ,  HECK, Howard L ,  JAUSSI, James E. ,  CASPER, Bryan K.

IPC: G06F13/14 ,  G06F1/26 ,  G06F1/04

CPC classification number: G06F1/26 ,  G06F1/266 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/3265 ,  G06F1/3278 ,  G06F1/3296 ,  G06F13/14 ,  G09G5/006 ,  G09G5/18 ,  G09G2330/021 ,  Y02D10/126 ,  Y02D10/153 ,  Y02D10/157 ,  Y02D10/172 ,  Y02D50/20

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.

Abstract translation: 互连设备的系统和方法可以包括具有一个或多个时钟电路的输入/输出（IO）接口，耦合到一个或多个时钟电路的电源和在IO接口处接收速率调整命令的逻辑。 逻辑还可以被配置为响应于速率调整命令来调整IO接口的数据速率，并且响应于速率调整命令来调整电源的输出电压。

公开(公告)号：WO2011081846A3

公开(公告)日：2011-07-07

申请号：PCT/US2010/059853

申请日：2010-12-10

Applicant: INTEL CORPORATION ,  DUNNING, Dave ,  CASPER, Bryan ,  MOONEY, Randy ,  MANSURI, Mozhgan ,  JAUSSI, James E.

Inventor： DUNNING, Dave ,  CASPER, Bryan ,  MOONEY, Randy ,  MANSURI, Mozhgan ,  JAUSSI, James E.

IPC: G11C5/02

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

公开(公告)号：WO2013070239A1

公开(公告)日：2013-05-16

申请号：PCT/US2011/060376

申请日：2011-11-11

Applicant: INTEL CORPORATION ,  MOONEY, Stephen, R. ,  HECK, Howard, L ,  JAUSSI, James, E. ,  CASPER, Bryan, K. ,  CHOUDHURY, Debabani ,  HADY, Frank, T.

Inventor： MOONEY, Stephen, R. ,  HECK, Howard, L ,  JAUSSI, James, E. ,  CASPER, Bryan, K. ,  CHOUDHURY, Debabani ,  HADY, Frank, T.

IPC: G06F1/00 ,  H04W92/02 ,  H04L29/10

CPC classification number: H04B1/40 ,  G06F13/4068 ,  G06F2213/0042

Abstract: Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts.

Abstract translation: 互连设备的系统和方法可以包括具有基板，一组输入/输出（IO）触点，天线结构和收发器逻辑的连接器组件。 在一个示例中，收发器逻辑可以处理与天线结构相关联的一个或多个IO信号并且处理与该组IO触点相关联的一个或多个IO信号。

公开(公告)号：WO2013048508A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054452

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  JAUSSI, James, E. ,  MOONEY, Stephen, R. ,  CASPER, Bryan, K. ,  HECK, Howard, L.

Inventor： JAUSSI, James, E. ,  MOONEY, Stephen, R. ,  CASPER, Bryan, K. ,  HECK, Howard, L.

IPC: G06F13/14 ,  G06F13/38

CPC classification number: H04L41/0896 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods of interconnecting devices may include an input/output (10) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device- side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device- side data lanes based on the bandwidth configuration command.

Abstract translation: 互连设备的系统和方法可以包括具有一个或多个设备侧数据通道的输入/输出（10）接口和用于接收带宽配置命令的收发机逻辑。 收发器逻辑还可以基于带宽配置命令来配置一个或多个设备侧数据通道的发送带宽。 此外，收发器逻辑可以基于带宽配置命令来配置一个或多个设备侧数据通道的接收带宽。