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    ON-PACKAGE INPUT/OUTPUT ARCHITECTURE
    2.
    发明申请
    ON-PACKAGE INPUT/OUTPUT ARCHITECTURE 审中-公开
    封装输入/输出结构

    公开(公告)号：WO2013095536A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/066971

    申请日：2011-12-22

    Applicant: INTEL CORPORATION ,  THOMAS, Thomas P. ,  KUMAR, Rajesh

    Inventor： THOMAS, Thomas P. ,  KUMAR, Rajesh

    IPC: G06F1/00 ,  G06F13/14

    CPC classification number: G06F13/4072 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4086 ,  H01L2924/0002 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2924/00

    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

    Abstract translation: 一个封装接口。 第一组第一组单端发射机电路。 发射机电路阻抗匹配，无均衡。 第二组芯片上的第一组单端接收器电路。 接收器电路没有终端，没有均衡。 多条导线耦合第一组发射机电路和第一组接收机电路。 多条导线的长度相匹配。

    LOW POWER, JITTER AND LATENCY CLOCKING WITH COMMON REFERENCE CLOCK SIGNALS FOR ON-PACKAGE INPUT/OUTPUT INTERFACES
    4.
    发明申请
    LOW POWER, JITTER AND LATENCY CLOCKING WITH COMMON REFERENCE CLOCK SIGNALS FOR ON-PACKAGE INPUT/OUTPUT INTERFACES 审中-公开
    低功耗，抖动和延迟时钟与通用输入/输出接口的通用参考时钟信号

    公开(公告)号：WO2013095549A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/066990

    申请日：2011-12-22

    Applicant: INTEL CORPORATION ,  KURD, Nasser A. ,  THOMAS, Thomas P.

    Inventor： KURD, Nasser A. ,  THOMAS, Thomas P.

    IPC: G06F1/00 ,  G06F1/04 ,  G06F13/14 ,  H03L7/08

    CPC classification number: H03L7/22 ,  G06F1/06 ,  G06F1/32

    Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.

    Abstract translation: 低功耗，抖动和延迟时钟，具有用于封装输入/输出接口的公共参考时钟信号。 第一管芯上的主器件中的滤波器锁相环电路提供具有2F频率的时钟信号。 第一管芯上的主器件中的本地锁相环电路与滤波器锁相环耦合，以通过本地时钟分频器电路为主器件的功能部件提供时钟信号，以向功能部件提供F的时钟信号 组件。 第二管芯上的从器件中的远程锁相环电路与滤波器锁相环耦合，以通过本地时钟分频器电路向从器件的一个或多个功能部件提供时钟信号，以提供F 到功能组件。

    ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DUPLEX MODES
    5.
    发明申请
    ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DUPLEX MODES 审中-公开
    具有全双工模式的封装输入/输出集群接口

    公开(公告)号：WO2013095542A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/066981

    申请日：2011-12-22

    Applicant: INTEL CORPORATION ,  THOMAS, Thomas P. ,  KULICK, Stanley S. ,  OSBORNE, Randy B.

    Inventor： THOMAS, Thomas P. ,  KULICK, Stanley S. ,  OSBORNE, Randy B.

    IPC: H04B1/40 ,  H04B14/02

    CPC classification number: G06F13/4068 ,  G06F13/4086 ,  G06F15/7825 ,  H03K19/017545 ,  H04B3/02 ,  H04B14/023

    Abstract: An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.

    Abstract translation: 一种用于控制片上网络流量的装置和系统。 该装置的实施例包括在第一芯片上用于与第二芯片耦合的单端传输电路和单端接收电路，所述传输电路具有阻抗匹配和缺少均衡，接收电路缺少均衡，传输电路和接收电路 具有静态可配置的特征并且被组织成簇，其中所述簇具有用于不同配置的可配置特征的相同的物理层电路设计，所述可配置特征包括半双工模式和全双工模式，其中第一芯片和第二芯片是 在相同的封装上，并且其中用于将第一芯片与第二芯片耦合的多条导线匹配。

    MECHANISMS FOR CLOCK GATING
    6.
    发明申请
    MECHANISMS FOR CLOCK GATING 审中-公开
    时钟效应机制

    公开(公告)号：WO2013095551A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/066993

    申请日：2011-12-22

    Applicant: INTEL CORPORATION ,  OSBORNE, Randy B. ,  KULICK, Stanley S. ,  FRANCOM, Erin ,  THOMAS, Thomas P.

    Inventor： OSBORNE, Randy B. ,  KULICK, Stanley S. ,  FRANCOM, Erin ,  THOMAS, Thomas P.

    IPC: G06F1/04 ,  G06F13/14

    CPC classification number: H03K5/15 ,  G06F1/06 ,  G06F1/10 ,  G06F1/32

    Abstract: Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.

    Abstract translation: 时钟门控机制。 时钟发生电路通过集成电路封装内的时钟信号分配网络提供时钟信号。 时钟信号分配网络内的选通元件将时钟信号禁止到时钟信号分配网络的一个或多个部分。 数字锁定环（DLL）在禁止时钟信号时保持设置而不进行跟踪。

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