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    METHOD AND CIRCUITS FOR SENSING ON-CHIP VOLTAGE IN POWERUP MODE
    2.
    发明申请
    METHOD AND CIRCUITS FOR SENSING ON-CHIP VOLTAGE IN POWERUP MODE 审中-公开
    用于在电源模式下感测片上电压的方法和电路

    公开(公告)号：WO2007118050A3

    公开(公告)日：2008-04-17

    申请号：PCT/US2007065782

    申请日：2007-04-02

    申请人： ATMEL CORP ,  CHAN JOHNNY ,  NG PHILIP

    发明人： CHAN JOHNNY ,  NG PHILIP

    IPC分类号： H01L23/62

    CPC分类号： H03K5/24

    摘要： A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input coupled to an internal node and a power connection coupled to a sensor power node. A circuit is configured to place a supply potential on the sensor power node when a threshold value is on the first pad. A switch coupled between the sensing circuit and the second pad turns on when the supply potential is on the voltage sensor power node.

    摘要翻译： 用于感测集成电路中的内部节点上的电压的方法包括将大于阈值的电压施加到第一焊盘，从激活电压产生感测电路的电位并耦合到内部节点，并将 当激活电压存在于第一焊盘上时，感测电路连接到集成电路上的第二焊盘。 感测电路包括第一和第二焊盘，具有耦合到内部节点的输入的电压传感器电路和耦合到传感器功率节点的电力连接。 电路被配置为当阈值位于第一焊盘上时，在传感器电源节点上放置电源。 当电源位于电压传感器功率节点上时，耦合在感测电路和第二焊盘之间的开关导通。

    METHOD OF SENSING AN EEPROM REFERENCE CELL
    3.
    发明申请
    METHOD OF SENSING AN EEPROM REFERENCE CELL 审中-公开
    传感EEPROM参考电池的方法

    公开(公告)号：WO2007018985A3

    公开(公告)日：2007-09-20

    申请号：PCT/US2006027914

    申请日：2006-07-18

    申请人： ATMEL CORP ,  CHAN JOHNNY ,  SON JINSHU ,  NG PHILIP S

    发明人： CHAN JOHNNY ,  SON JINSHU ,  NG PHILIP S

    IPC分类号： G11C16/04

    CPC分类号： G11C16/28

    摘要： An array (200; 202) of memory cells having a predetermined group (301) of storage cells (203; 205; 306) , arranged in a row, also have an arrangement of one or more reference cells (201; 207; 304, 307) fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the storage cells are written to, erased, or programmed. The same number of write, erase, or program cycles and the proximity of the reference cells to the storage cells maintain an operational matching of the storage cells and reference cells.

    摘要翻译： 具有排列成行的存储单元（203; 205; 306）的预定组（301）的存储单元的阵列（200; 202）也具有一个或多个参考单元（201; 207; 304， 307）被制造成与存储单元行相邻或邻近。 当存储单元写入，擦除或编程时，参考单元被写入，擦除或编程。 相同数量的写，擦除或程序周期以及参考单元与存储单元的接近度保持了存储单元和参考单元的操作匹配。

    CHARGE PUMP FOR INTERMEDIATE VOLTAGE
    4.
    发明申请
    CHARGE PUMP FOR INTERMEDIATE VOLTAGE 审中-公开
    充电电压用于中间电压

    公开(公告)号：WO2007062354A2

    公开(公告)日：2007-05-31

    申请号：PCT/US2006061109

    申请日：2006-11-20

    申请人： ATMEL CORP ,  CHAN JOHNNY ,  WONG TIN WAI ,  YE KEN KUN

    发明人： CHAN JOHNNY ,  WONG TIN WAI ,  YE KEN KUN

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07

    摘要： A charge pump generates a voltage higher than an intermediate voltage and a regulator circuit provides a first regulated voltage higher than the intermediate voltage. A second stage includes a regulator stage using the first voltage to provide the intermediate voltage from the first voltage. A charge pump provides a pump output voltage. The pump output voltage is divided and the divided voltage is presented to a first comparator that compares it with a reference voltage. The first comparator drives the gate of a first MOS transistor to regulate the pump output voltage to a regulated voltage related to the reference voltage. The regulated voltage is presented to a second comparator that compares it with the reference voltage. The second comparator drives the gate of a second MOS transistor to downconvert the regulated output voltage to an intermediate voltage related to the reference voltage.

    摘要翻译： 电荷泵产生高于中间电压的电压，并且调节器电路提供高于中间电压的第一调节电压。 第二级包括使用第一电压从第一电压提供中间电压的调节器级。 电荷泵提供泵输出电压。 泵浦输出电压被分压，并将分压提供给第一个比较器，将其与参考电压进行比较。 第一比较器驱动第一MOS晶体管的栅极，以将泵输出电压调节到与参考电压相关的调节电压。 调节电压被提供给第二个比较器，将其与参考电压进行比较。 第二比较器驱动第二MOS晶体管的栅极将调节的输出电压下变频到与参考电压相关的中间电压。

    REDUCTION OF PROGRAMMING TIME IN ELECTRICALLY PROGRAMMABLE DEVICES
    5.
    发明申请
    REDUCTION OF PROGRAMMING TIME IN ELECTRICALLY PROGRAMMABLE DEVICES 审中-公开
    减少电气可编程器件中的编程时间

    公开(公告)号：WO2007018913A2

    公开(公告)日：2007-02-15

    申请号：PCT/US2006/026925

    申请日：2006-07-10

    申请人： ATMEL CORPORATION ,  CHAN, Johnny ,  TSAI, Jeffrey, Ming-Hung ,  WONG, Tin-Wai

    发明人： CHAN, Johnny ,  TSAI, Jeffrey, Ming-Hung ,  WONG, Tin-Wai

    IPC分类号： G11C16/04

    CPC分类号： G11C16/16

    摘要： A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data "one” value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data "zero" is to be applied to the bit cell, a charge pump engages to bias the cell and activate a hot electron injection process to affect the programming. If a data "one" is to be applied to the bit cell, no programming activity is undertaken and the process increments to the next bit cell in the data structure. Therefore, total programming time is reduced proportionally to the number of data "one" bits to be programmed. Where more than one charge pump is engaged in parallel to a data structure, total programming time is further reduced when two data "one" values are to be programmed in parallel.

    摘要翻译： 闪存编程过程包含每位字节的两个电荷泵。 在每个位单元中放置数据“一个”值会擦除整个存储器件。 在对每个单元进行编程之前，仔细检查一个预期的数据内容。 如果将数据“零”应用于位单元，则电荷泵接合以偏置电池并激活热电子注入过程以影响编程。 如果将数据“1”应用于比特单元，则不进行编程活动，并且该处理在数据结构中递增到下一比特单元。 因此，总编程时间与要编程的数据“1”位的数量成比例地减小。 在多个电荷泵与数据结构并联的情况下，当两个数据“一个”值被并行编程时，总编程时间进一步减少。

    GEMSTONE ILLUMINATOR
    7.
    发明申请
    GEMSTONE ILLUMINATOR 审中-公开
    GEMSTONE照明器

    公开(公告)号：WO2015001490A1

    公开(公告)日：2015-01-08

    申请号：PCT/IB2014/062774

    申请日：2014-07-01

    申请人： CHAN, Johnny Yat Ming ,  WONG, Sun Fai Oskar

    发明人： CHAN, Johnny Yat Ming ,  WONG, Sun Fai Oskar

    IPC分类号： A44C11/00 ,  A44C9/00 ,  A44C25/00 ,  A44C17/00

    CPC分类号： H05B37/0272 ,  F21S9/02 ,  F21V33/0008 ,  H05B33/086 ,  H05B33/0872

    摘要： Devices and methods are disclosed for illuminating gemstones on fashion accessories a variety of colors. The device may process certain inputs to determine the color emanating from a light source that will illuminate the gemstone. The device may be integrated with a mobile application that wirelessly controls the color of the gemstone through a wireless connection to a light source. The device advantageously will allow input from the microphone or camera of the mobile device to change the color of the gemstone based on the ambient light or sound.

    摘要翻译： 公开了用于照亮各种颜色的时尚配饰上的宝石的装置和方法。 设备可以处理某些输入以确定从照亮宝石的光源发出的颜色。 该设备可以与通过无线连接到光源无线地控制宝石的颜色的移动应用集成。 该装置有利地允许来自移动装置的麦克风或照相机的输入基于环境光或声音来改变宝石的颜色。

    METHOD AND APPARATUS FOR IMPLEMENTING WALKOUT OF DEVICE JUNCTIONS
    9.
    发明申请
    METHOD AND APPARATUS FOR IMPLEMENTING WALKOUT OF DEVICE JUNCTIONS 审中-公开
    用于实施设备结点的方法和装置

    公开(公告)号：WO2007065108A3

    公开(公告)日：2009-01-15

    申请号：PCT/US2006061349

    申请日：2006-11-29

    申请人： ATMEL CORP ,  NG PHILIP S ,  SON JINSHU ,  CHAN JOHNNY

    发明人： NG PHILIP S ,  SON JINSHU ,  CHAN JOHNNY

    IPC分类号： G05F1/10

    CPC分类号： G11C5/145 ,  G11C5/147

    摘要： A high-voltage charge pump circuit includes a charge pump circuit. First high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high- voltage output circuits to the output of the high-voltage charge pump circuit.

    摘要翻译： 高压电荷泵电路包括电荷泵电路。 第一高电压输出电路被配置为将电荷泵的输出电压设置在为正常编程和擦除存储器单元所选择的第一电压电平。 第二高电压输出电路被配置为将电荷泵的输出电压设置为选择用于器件结的去除的第二电压电平，第二电压电平高于第一电压电平。 第三高压输出电路被配置为将电荷泵的输出电压设置为选择用于保护带编程和擦除的第三电压电平，第三电压电平低于第二电压电平并高于第一电压电平。 选择电路将第一，第二和第三高压输出电路中的一个选择性地耦合到高压电荷泵电路的输出。

    LEAKAGE IMPROVEMENT FOR A HIGH-VOLTAGE LATCH
    10.
    发明申请
    LEAKAGE IMPROVEMENT FOR A HIGH-VOLTAGE LATCH 审中-公开

    公开(公告)号：WO2008030812A3

    公开(公告)日：2008-03-13

    申请号：PCT/US2007/077542

    申请日：2007-09-04

    申请人： ATMEL CORPORATION ,  CHAN, Johnny ,  TSAI, Jeffrey, Ming-Hung ,  WONG, Tin-Wai

    发明人： CHAN, Johnny ,  TSAI, Jeffrey, Ming-Hung ,  WONG, Tin-Wai

    IPC分类号： G11C7/10

    摘要： An improved CMOS high-voltage latch (100) stores data bits to be written to memory cells of a non- volatile memory has two cross- coupled CMOS inverters (102, 104). One inverters (104) has a pull-down leg that includes a pass-gate high-voltage NMOS transistor (116) connected between a latch output node and a second high-voltage, low-threshold NMOS pull- down transistor (118), connected to ground. A gate of the NMOS transistor (116) receives a standby signal with a logic HIGH value to turn on the NMOS transistor (116) when the CMOS latch (100) is in a data-loading mode of operation and during a high-voltage write mode of operation. The NMOS transistor (118) thereby limits the voltage across the second NMOS pull-down transistor (118) to less than the standby signal, reducing punch-through current and drain-to-substrate leakage from second NMOS pull-down transistor (118).