公开(公告)号：WO2021005171A1

公开(公告)日：2021-01-14

申请号：PCT/EP2020/069424

申请日：2020-07-09

申请人： ABB POWER GRIDS SWITZERLAND AG

发明人： WEISS, David ,  DUERR, Mathias ,  FUCHS, Stefan

IPC分类号： H01L23/62 ,  H01L25/11

摘要： A power semiconductor module (12) comprises a plurality of power semiconductor chips (36), each of which provides at least one power semiconductor switch; a housing (44) for accommodating the power semiconductor chips (36); at least one first module electrode (18) on a first side (48) of the housing (44) electrically connected to a first chip electrode (37) of the power semiconductor chips (36); at least one second module electrode (20) on a second side (52) of the housing (44) electrically connected to a second chip electrode (39) of the power semiconductor chips (36), which second side (52) of the housing (44) is opposite to the first side (48); and a surge arrester arrangement (60) with a surge arrester (38) accommodated in the housing (44), such that a first electrode (74) of the surge arrester arrangement (60) is provided at the first side (48) of the housing (44) and a second electrode (76) of the surge arrester arrangement (60) is provided at the second side (52) of the housing (44). The plurality of power semiconductor chips (36) are arranged in an annular region (62) in the housing (44) and the surge arrester arrangement (60) is arranged within the annular region (62).

公开(公告)号：WO2020114660A1

公开(公告)日：2020-06-11

申请号：PCT/EP2019/078249

申请日：2019-10-17

申请人： ABB SCHWEIZ AG

发明人： COTTET, Didier ,  KICIN, Slavo

IPC分类号： H01L23/62 ,  H01L25/07

摘要： A power semiconductor module comprises a base plate (1); a semiconductor chip (2) disposed on and in contact with a top surface of the base plate (1), a preform (3) disposed on and in contact with a top surface of the semiconductor chip (2); and a pressing element (4) in contact with and applying a pressure onto a top surface of the preform (3). The preform (3) comprises a first electrically conductive layer (6) and a second electrically conductive layer (5). The first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining a recess (9) in the first electrically conductive layer (6) of the preform (3), wherein the recess (9) may annularly surround the protrusion (7). The at least one protrusion (7) is made from the same material as the first electrically conducting layer (6) and integrally formed with it or the first electrically conducting layer (6) and the at least one protrusion (7) are made from different materials. At least a portion of the second electrically conductive layer (5) is positioned in the recess (9) and on the top surface of the semiconductor chip (2). The material of the at least one protrusion (7) has a higher melting point than the material of the second electrically conductive layer (5). The power semiconductor module is configured so that in an event of semiconductor chip failure with heat dissipation, the protrusion (7) of the first electrically conductive layer (6) penetrates through residual material (8) of the semiconductor chip (2) upon pressure applied by the pressing element (4) towards the base plate (1) so as to establish a contact between the protrusion (7) of the first electrically conductive layer (6) and the base plate (1) and form a short circuit bridging the defective semiconductor chip (2) in a short circuit failure mode. The bottom surface of the preform (3) may be formed by a bottom surface of the second electrically conductive layer (5) alone or by a bottom surface of the second electrically conductive layer (5) and a bottom surface of the protrusion (7).

公开(公告)号：WO2020030757A1

公开(公告)日：2020-02-13

申请号：PCT/EP2019/071361

申请日：2019-08-08

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： BUCKLEY, Julien ,  ESCOFFIER, René

IPC分类号： H01L23/525 ,  H01L29/417 ,  H01L23/62 ,  H01L29/778

摘要： La présente invention se rapporte à un transistor à effet de champ (100) comportant : − un substrat (1); − une structure semi-conductrice (2) formée sur une face principale du substrat (1), la structure semi-conductrice (2) comprenant une zone de canal (7); − une première électrode (3) et une deuxième électrode (4) entre lesquelles s'étend la zone de canal (7), la première électrode (3) comportant une pluralité de portions (30) espacées les unes des autres, chaque portion (30) de la première électrode (3) contribuant à former un transistor élémentaire appelé « îlot »; − des pistes de connexion (36) pour connecter électriquement les portions (30) de la première électrode (3) entre elles; et dans lequel chaque portion (30) de la première électrode (3) est connectée à une piste de connexion (36) par l'intermédiaire d'une zone fusible (9), chaque zone fusible (9) associée à la portion (30) de la première électrode (3) d'un îlot étant apte à être rompue de manière à isoler électriquement ledit îlot s'il est défectueux.

公开(公告)号：WO2019185559A3

公开(公告)日：2019-10-03

申请号：PCT/EP2019/057472

申请日：2019-03-25

申请人： ANALOG DEVICES GLOBAL UNLIMITED COMPANY

发明人： CLARKE, David J. ,  HEFFERNAN, Stephen Denis ,  WEI, Nijun ,  O'DONNELL, Alan J. ,  MCGUINNESS, Patrick Martin ,  BRADLEY, Shaun ,  COYNE, Edward John ,  AHERNE, David ,  BOLAND, David M.

IPC分类号： G01R31/00 ,  H01L23/60 ,  H01L23/62 ,  H02H9/00

摘要： The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event.The two conductive structures have facing surfaces that have different shapes;

公开(公告)号：WO2019066879A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054185

申请日：2017-09-28

申请人： INTEL CORPORATION ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak ,  TRONIC, Tristan A. ,  PAUL, Rajat K.

发明人： THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak ,  TRONIC, Tristan A. ,  PAUL, Rajat K.

IPC分类号： H01L23/525 ,  H01L23/62

摘要： Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.

公开(公告)号：WO2018224618A1

公开(公告)日：2018-12-13

申请号：PCT/EP2018/065088

申请日：2018-06-07

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： STEGMEIER, Stefan ,  BERTHOLD, Thomas ,  SCHMITT, Daniel ,  SCHREMMER, Frank

IPC分类号： H01L23/62 ,  H01L23/051 ,  H01L21/60

摘要： Ein leistungselektronisches Schaltmodul umfasst mindestens einen Leistungshalbleiter (20) und einen an dem Leistungshalbleiter (20) elektrisch anbindbaren oder angebundenen ersten Schaltkontakt (30) und einen an dem Leistungshalbleiter elektrisch anbindbaren oder angebundenen zweiten Schaltkontakt (10), wobei erster (30) und zweiter Schaltkontakt (10) zumindest in einem Bereich zueinander kraftbeaufschlagt und mittels einer elektrischen Isolation (40) voneinander beabstandet sind, wobei die Isolation (40) derart angeordnet und ausgebildet ist, dass sie infolge Bestromung des Leistungshalbleiters (20) mit einem Fehlerstrom dort entfernbar ist, wo die Isolation (40) bei ausbleibender Bestromung den ersten und den zweiten Schaltkontakt (10, 30) voneinander beabstandet. Folglich werden der erste und der zweite Schaltkontakt (10, 30) im Fehlerfall nicht weiter durch die Isolation (40) beabstandet und können aufgrund der Kraftbeaufschlagung aufeinander zu miteinander elektrisch leitend in Kontakt treten und einen alternativen Fehlerstrompfad ausbilden.

公开(公告)号：WO2018125223A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069532

申请日：2016-12-30

申请人： INTEL CORPORATION

发明人： BAINS, Balijeet S. ,  WALLACE, Charles H. ,  CHEN, Zhanping

IPC分类号： H01L23/525 ,  H01L23/62 ,  H01L21/768

摘要： Embodiments herein describe techniques for fuse lines and plugs formation. A semiconductor device may include a fuse line having a nominal fuse segment abutted to a necked fuse segment. The nominal fuse segment may be wider than the necked fuse segment. A first spacer may be along a first side of the fuse line and a second spacer along a second side opposite to the first side of the fuse line. The first spacer may include a part having a width at least twice a width of a part of the second spacer. A plug within a vicinity of the necked fuse segment may have a plug width that may be at least twice a plug with of a plug of an interconnect line outside the vicinity. Other embodiments may also be described and claimed.

公开(公告)号：WO2018004821A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/030886

申请日：2017-05-03

申请人： INTEL CORPORATION

发明人： BROWNE, John J. ,  MACLEAN, Andrew ,  LIFF, Shawna M.

IPC分类号： H01L23/525 ,  H01L23/62 ,  H01L23/48

CPC分类号： H05K3/34 ,  G06F13/00 ,  H05K1/0293 ,  H05K1/141 ,  H05K2201/0305 ,  H05K2201/042 ,  H05K2201/09036 ,  H05K2201/10181 ,  H05K2201/10189 ,  H05K2201/10212 ,  H05K2203/1115 ,  H05K2203/173

摘要： Techniques and mechanisms for controlling configurable circuitry including an antifuse. In an embodiment, the antifuse is disposed in or on a substrate, the antifuse configured to form a solder joint to facilitate interconnection of circuit components. Control circuitry to operate with the antifuse is disposed in, or at a side of, the same substrate. The antifuse is activated based on a voltage provided at an input node, where the control circuitry automatically transitions through a pre-determined sequence of states in response to the voltage. The pre-determined sequence of states coordinates activation of one or more fuses and switched coupling one or more circuit components to the antifuse. In another embodiment, multiple antifuses, variously disposed in or on the substrate, are configured each to be activated based on the voltage provided at an input node.

摘要翻译： 用于控制包括反熔丝的可配置电路的技术和机制。 在一个实施例中，反熔丝被设置在衬底中或衬底上，反熔丝被配置成形成焊点以促进电路元件的互连。 与反熔丝一起操作的控制电路设置在同一衬底中或同一衬底的一侧。 基于在输入节点处提供的电压激活反熔丝，其中控制电路响应于电压而自动转换通过预定状态序列。 预定的状态序列协调一个或多个熔断器的激活并将一个或多个电路部件切换耦合到反熔丝。 在另一个实施例中，不同地设置在衬底中或衬底上的多个反熔丝被配置为每一个都基于在输入节点处提供的电压而被激活。

公开(公告)号：WO2017208343A1

公开(公告)日：2017-12-07

申请号：PCT/JP2016/066026

申请日：2016-05-31

申请人： 三菱電機株式会社

发明人： 西村　一廣 ,  河本　厚信 ,  山本　剛司

IPC分类号： H01L23/62 ,  H01L23/00 ,  H01L23/48

摘要： 　高圧電極（５）の一端が半導体素子（１）の高圧端子に接続されている。低圧電極（６）の一端が半導体素子（１）の低圧端子に接続されている。樹脂（１５）が半導体素子（１）、高圧電極（５）の一端、及び低圧電極（６）の一端を封止する。第１及び第２の放電電極（１６，１７）が、高圧電極（５）及び低圧電極（６）の樹脂（１５）で覆われていない部分にそれぞれ設けられ、互いに対向するように突出している。

摘要翻译： 高压电极（5）的一端连接到半导体元件（1）的高电压端子。 低压电极（6）的一端连接到半导体元件（1）的低压端子。 树脂（15）密封半导体元件（1），高压电极（5）的一端和低压电极（6）的一端。 设置在每个未包括的高电压电极（5）和所述低压电极（15）部分的树脂的第一和第二放电电极（16,17）（6），突出以便彼此面对 。

公开(公告)号：WO2017057844A1

公开(公告)日：2017-04-06

申请号：PCT/KR2016/008711

申请日：2016-08-08

申请人： 삼성에스디아이 주식회사

发明人： 이윤만 ,  배경철 ,  엄태신 ,  이동환 ,  이영균 ,  이은정

IPC分类号： H01L23/60 ,  H01L23/28 ,  H01L23/62 ,  H01L23/00

CPC分类号： H01L23/00 ,  H01L23/28 ,  H01L23/60 ,  H01L23/62 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15159 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： 본 발명은 회로 기판, 상기 회로 기판 상에 실장되는 적어도 하나 이상의 반도체 칩, 상기 반도체 칩을 밀봉하는 제1밀봉층 및 상기 제1밀봉층 상부에 니켈을 함유하는 퍼말로이 및 탄소나노튜브를 포함하는 에폭시 수지 조성물에 의해 형성되는 제2밀봉층을 포함하는 반도체 패키지 및 그 제조방법에 관한 것이다.

摘要翻译： 本发明涉及一种半导体器件，包括：电路板; 安装在电路板上的至少一个半导体芯片; 用于密封半导体芯片的第一密封层; 以及由在第一密封层上含有含有坡莫合金和含有镍的碳纳米管的环氧树脂组合物形成的第二密封层及其制造方法。