公开(公告)号：WO2008141098A3

公开(公告)日：2009-01-29

申请号：PCT/US2008063085

申请日：2008-05-08

Applicant: CHAOLOGIX INC ,  SCHEIDERWIND ROBERT A

Inventor： SCHEIDERWIND ROBERT A

IPC: H03K19/173

CPC classification number: H03K19/1733 ,  G06N7/08

Abstract: A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.

Abstract translation: 动态可配置的逻辑门包括用于接收第一输入信号的输入加法器和用于产生求和的输入信号的第二输入信号。 此外，动态可配置逻辑门包括非线性元件，其将非线性函数应用于求和的输入信号以产生非线性输出信号。 响应于调整相加的输入信号和/或非线性函数，可动态配置的逻辑门输出信号对应于多个不同逻辑门中的一个。 在另一个实施例中，动态可配置的逻辑门包括对其中一个输入的反馈。 动态可配置的逻辑门接收两个输入并且作为多个不同的逻辑门类型之一进行操作，以根据控制信号的选择产生对应于存储器锁存器的输出信号。 还公开了可动态配置的逻辑元件的阵列结构。

公开(公告)号：WO2014074355A8

公开(公告)日：2014-05-15

申请号：PCT/US2013/067391

申请日：2013-10-30

Applicant: CHAOLOGIX, INC.

Inventor： YANNETTE, Daniel, F. ,  MYERS, Brent, Arnold

IPC: G06F21/00 ,  G06F21/70

Abstract: Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

公开(公告)号：WO2011047035A2

公开(公告)日：2011-04-21

申请号：PCT/US2010052489

申请日：2010-10-13

Applicant: CHAOLOGIX INC ,  MYERS BRENT A ,  FOX JAMES G

Inventor： MYERS BRENT A ,  FOX JAMES G

IPC: H03K19/173 ,  H03K19/00

CPC classification number: H03K19/17768 ,  G06F21/755 ,  H01L2924/0002 ,  H03K19/0013 ,  H03K19/0944 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/20 ,  H04L9/001 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12 ,  H01L2924/00

Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.

Abstract translation: 公开了一种能够根据输入逻辑信号产生可能的任何逻辑组合的新颖电路。 该电路被描述为2输入逻辑映射电路，但可根据需要扩展到3个或更多输入。 还公开了具有可变电路拓扑结构的通用逻辑阵列。 阵列元件中的单元之间的金属化层和/或通孔互连产生实现布尔函数和/或混沌功能和/或逻辑功能的电路布局。 该新型电路为安全应用提供电路拓扑结构，控制信号值与输入到输出映射之间没有明显的物理对应关系。 还公开了一种具有与输入信号状态和输出转换无关的功率特征的网络。 这提供了一个非常有用的电路来保护数据免受安全应用程序中的功率签名分析的解密。

公开(公告)号：WO2017139241A1

公开(公告)日：2017-08-17

申请号：PCT/US2017/016771

申请日：2017-02-07

Applicant: CHAOLOGIX, INC.

Inventor： YANAMADALA, Subbayya Chowdary ,  YANNETTE, Daniel F. ,  MYERS, Brent Arnold

IPC: G05F1/59 ,  G06F21/00 ,  G06F21/55 ,  G06F21/70 ,  G06F21/72 ,  G06F21/74

CPC classification number: G05F1/59 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Abstract translation: 提供功率规划阶段模块，放置阶段模块和路由阶段模块，其可以替代，补充或增强现有的电子设计自动化（EDA）软件工具。 功率规划阶段模块将分布式功率源和交换元件网络添加到分配给芯片区域（可以在楼层规划阶段期间识别的）的功率帧或环上。 配置阶段模块优化了在功率规划阶段期间已经添加或将要添加的分布式电源的每个电源附加的电池的数量和类型。 路由选择阶段模块优化路由长度，例如掩码功耗。

公开(公告)号：WO2014074355A1

公开(公告)日：2014-05-15

申请号：PCT/US2013/067391

申请日：2013-10-30

Applicant: CHAOLOGIX, INC.

Inventor： YANNETTE, Daniel, F. ,  MYERS, Brent, Arnold

IPC: G06F21/00 ,  G06F21/70

CPC classification number: H03K19/003 ,  G06F21/75 ,  G09C1/00 ,  H03K19/17768 ,  H04L9/003 ,  H04L2209/12

Abstract: Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

Abstract translation: 提供有利的数字逻辑单元和使用其的逻辑块供电的方法。 数字逻辑单元可以包括电荷存储装置，逻辑块和到电源的连接。 电荷存储装置可以是电容器。 电容器或其他电荷存储装置可以从逻辑块和电源断开，放电电容器，然后通过电源连接器连接到电源，为电容充电。 当电容器放电时，电容器可以与电源的接地连接断开。 通过电源充电后，电容器也可以与电源（包括地）断开连接，并连接到逻辑块以为逻辑块供电。

公开(公告)号：WO2014193496A1

公开(公告)日：2014-12-04

申请号：PCT/US2014/017369

申请日：2014-02-20

Applicant: CHAOLOGIX, INC.

Inventor： YANNETTE, Daniel, F. ,  MYERS, Brent, Arnold

IPC: G06F21/72 ,  G06K19/073 ,  H04L9/00 ,  H03K19/177

CPC classification number: H04L9/003 ,  G06F21/72 ,  G06F21/75 ,  G06K19/073 ,  G09C1/00 ,  H03K19/17768 ,  H04L2209/12

Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device (12), a logic block (10), and connections to a power supply (14). The charge storage device may be a capacitor (12). The capacitor or other charge storage device (12) can be disconnected from the logic block (10) and a power supply (14) to discharge the capacitor (12), and then connected to the power supply (14), via the power supply connections (18, 20), to charge the capacitor (12). The capacitor (12) can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply (14), the capacitor (12) can also be disconnected from the power supply (14), including ground, and connected to the logic block (10) to power the logic block.

Abstract translation: 提供有利的模拟和/或数字逻辑单元以及使用其的电路块供电的方法。 数字逻辑单元可以包括电荷存储装置（12），逻辑块（10）以及到电源（14）的连接。 电荷存储装置可以是电容器（12）。 电容器或其他电荷存储装置（12）可以与逻辑块（10）和电源（14）断开，以对电容器（12）进行放电，然后通过电源连接到电源（14） 连接（18,20），以对电容器（12）充电。 当电容器放电时，电容器（12）可以与电源的接地连接断开。 在通过电源（14）充电之后，电容器（12）也可以与包括接地的电源（14）断开连接，并连接到逻辑块（10）以为逻辑块供电。

公开(公告)号：WO2011047035A3

公开(公告)日：2011-04-21

申请号：PCT/US2010/052489

申请日：2010-10-13

Applicant: CHAOLOGIX, INC. ,  MYERS, Brent, A. ,  FOX, James, G.

Inventor： MYERS, Brent, A. ,  FOX, James, G.

IPC: H03K19/173 ,  H03K19/00

Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.

公开(公告)号：WO2008079964A1

公开(公告)日：2008-07-03

申请号：PCT/US2007/088356

申请日：2007-12-20

Applicant: CHAOLOGIX, INC. ,  KIEL, Steven, Lee ,  KRENING, Douglas, Norman ,  LEHMAN, Lark, Edward ,  SCHNEIDERWIND, Michael, Joseph

Inventor： KIEL, Steven, Lee ,  KRENING, Douglas, Norman ,  LEHMAN, Lark, Edward ,  SCHNEIDERWIND, Michael, Joseph

IPC: G06F7/57

CPC classification number: H03K19/173 ,  H03K3/037

Abstract: A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.

Abstract translation: 动态可配置的逻辑门包括用于接收第一输入信号的输入加法器和用于产生求和的输入信号的第二输入信号。 此外，动态可配置逻辑门包括非线性元件，其将非线性函数应用于求和的输入信号以产生非线性输出信号。 响应于调整相加的输入信号和/或非线性函数，可动态配置的逻辑门输出信号对应于多个不同逻辑门中的一个。 在另一个实施例中，动态可配置的逻辑门包括对其中一个输入的反馈。 动态可配置的逻辑门接收两个输入并且作为多个不同的逻辑门类型之一进行操作，以根据控制信号的选择产生对应于存储器锁存器的输出信号。 还公开了可动态配置的逻辑元件的阵列结构。

公开(公告)号：WO2017083797A1

公开(公告)日：2017-05-18

申请号：PCT/US2016/061732

申请日：2016-11-13

Applicant: CHAOLOGIX, INC.

Inventor： MILIOTIS, Abraham

IPC: H03M7/30

CPC classification number: H03M7/30 ,  H03M7/3097 ,  H03M7/55

Abstract: A data compression system can include a compression unit comprising a single chaotic system having an identified initial condition that produces a desired output sequence of data corresponding to a data set being stored. The single chaotic system can be identified using a chain of controlled nonlinear systems and a dynamical search technique to match the output, in sequence over consecutive time intervals with the chain of the controlled nonlinear systems.

Abstract translation: 数据压缩系统可以包括压缩单元，该压缩单元包括具有识别的初始条件的单个混沌系统，该初始条件产生对应于被存储的数据集的期望输出数据序列。 单个混沌系统可以使用一系列受控的非线性系统和一个动态搜索技术来识别，以便在连续的时间间隔内与受控非线性系统链顺序地匹配输出。

公开(公告)号：WO2016007501A1

公开(公告)日：2016-01-14

申请号：PCT/US2015/039364

申请日：2015-07-07

Applicant: CHAOLOGIX, INC.

Inventor： BELL, Timothy Arthur ,  MYERS, Brent Arnold

IPC: G09C1/00 ,  H04L9/00

CPC classification number: H03K19/003 ,  G05F1/59 ,  G09C1/00 ,  H03K19/0948 ,  H04L9/003 ,  H04L9/004 ,  H04L9/005 ,  H04L2209/12

Abstract: A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply.

Abstract translation: 描述了用于从外部电源接口安全地隔离电路的浮动核心网络。 核心的隔离通过动态限流网络来实现，该网络向核心提供隔离的核心电压; 以及由动态限流网络连续再充电的相应核心的隔离电源。 动态限流网络可以包括两个控制环路，一个控制环路向提供给隔离电源的电流的p型晶体管提供固定的栅极电压，另一个控制环路为从n型晶体管提供固定的栅极电压， 隔离供应。