公开(公告)号：WO2020236290A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/024271

申请日：2020-03-23

Applicant: CRAY INC.

Inventor： BATAINEH, Abdulla M. ,  COURT, Thomas L. ,  HODGE, Hess M.

IPC: G06F12/1045 ,  G06F12/0862 ,  G06F12/0888 ,  H04L12/861

Abstract: A network interface controller (NIC) capable of facilitating efficient memory address translation is provided. The NIC can be equipped with a host interface, a cache, and an address translation unit (ATU). During operation, the ATU can determine an operating mode. The operating mode can indicate whether the ATU is to perform a memory address translation at the NIC. The ATU can then determine whether a memory address indicated in the memory access request is available in the cache. If the memory address is not available in the cache, the ATU can perform an operation on the memory address based on the operating mode.

公开(公告)号：WO2020236288A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/024269

申请日：2020-03-23

Applicant: CRAY INC.

Inventor： ALVERSON, Robert L. ,  KOPSER, Andrew S.

IPC: H04L12/931 ,  H04L12/933 ,  H04L12/911 ,  H04L12/861

Abstract: A switch capable of on-the-fly reduction in a network is provided. The switch is equipped with a reduction engine that can be dynamically configured to perform on-the-fly reduction. As a result, the network can facilitate an efficient and scalable environment for high performance computing.

公开(公告)号：WO2020236284A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/024262

申请日：2020-03-23

Applicant: CRAY INC.

Inventor： ALVERSON, Robert L. ,  KUNDU, Partha ,  ROWETH, Duncan ,  HEWSON, David Charles ,  CHENG, Albert

IPC: H04L12/805 ,  H04L12/801 ,  H04L12/861 ,  G06F3/06

Abstract: A network interface controller (NIC) capable of efficient packet forwarding is provided. The NIC can be equipped with a host interface, a packet generation logic block, and a forwarding logic block. During operation, the packet generation logic block can obtain, via the host interface, a message from the host device and for a remote device. The packet generation logic block may generate a plurality of packets for the remote device from the message. The forwarding logic block can then send a first subset of packets of the plurality of packets based on ordered delivery. If a first condition is met, the forwarding logic block can send a second subset of packets of the plurality of packets based on unordered delivery. Furthermore, if a second condition is met, the forwarding logic block can send a third subset of packets of the plurality of packets based on ordered delivery.

公开(公告)号：WO2020236273A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/024246

申请日：2020-03-23

Applicant: CRAY INC.

Inventor： GORODETSKY, Igor ,  ROWETH, Duncan

IPC: H04L12/835 ,  H04L12/801 ,  H04L12/861 ,  H04L12/851

Abstract: A network interface controller (NIC) capable of hybrid message matching is provided. The NIC can be equipped with a host interface, a hardware endpoint, and an endpoint management logic block. The host interface can couple the NIC to a host device. The hardware endpoint can facilitate a point of communication for an application running on the host device. The endpoint management logic block can maintain a list for storing a message associated with an endpoint represented by the hardware endpoint. The endpoint management logic block can then determine whether the utilization of the list is higher than a threshold. If the utilization is higher than the threshold, the endpoint management logic block can set a state of the endpoint to indicate that the endpoint is software managed. The NIC thus can transfer the control of the endpoint from the hardware endpoint to a software process of the host device.

公开(公告)号：WO2020236271A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/024244

申请日：2020-03-23

Applicant: CRAY INC.

Inventor： HODGE, Hess M. ,  GORODETSKY, Igor

IPC: G06F12/1009 ,  G06F12/1045 ,  G06F13/16 ,  G06F13/24 ,  G06F13/28

Abstract: A network interface controller (NIC) capable of on-demand paging is provided. The NIC can be equipped with a host interface, an operation logic block, and an address logic block. The host interface can couple the NIC to a host device. The operation logic block can obtain from a remote device, a request for an operation based on a virtual memory address. The address logic block can obtain, from the operation logic block, a request for an address translation for the virtual memory address and issue an address translation request to the host device via the host interface. If the address translation is unsuccessful, the address logic block can send a page request to a processor of the host device via the host interface. The address logic block can then determine that a page has been allocated in response to the page request and reissue the address translation request.

公开(公告)号：WO2020236270A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/024243

申请日：2020-03-23

Applicant: CRAY INC.

Inventor： BEECROFT, Johnathan P. ,  ALVERSON, Robert L. ,  TURNER, Edward J.

IPC: H04L12/931 ,  H04L12/841 ,  H04L12/935 ,  H04L29/06

Abstract: A switch equipped with a self-managing reduction engine is provided. During operation, the reduction engine can use a timeout mechanism to manage itself in different latency-induced or error scenarios. As a result, the network can facilitate an efficient and scalable environment for high performance computing.

公开(公告)号：WO2020236262A2

公开(公告)日：2020-11-26

申请号：PCT/US2020/024170

申请日：2020-03-23

Applicant: CRAY INC.

Inventor： BATAINEH, Abdulla M. ,  FROESE, Edwin L. ,  ROWETH, Duncan

IPC: H04L12/721

Abstract: A switch is provided, which can receive a data communication at an edge of a network. The network may be made up of a plurality of switches. The switch may generate a flow channel based upon an identified source and destination for the data communication. The data communication can be routed across the plurality of switches based on minimizing a number of hops between a subset of the plurality of switches and in accordance with the flow channel.

公开(公告)号：WO2005119410A3

公开(公告)日：2006-04-27

申请号：PCT/US2005019597

申请日：2005-06-03

Applicant: CRAY INC ,  HELLRIEGEL STEPHEN V R ,  YATSKOV ALEXANDER I ,  KELLEY DOUGLAS P

Inventor： HELLRIEGEL STEPHEN V R ,  YATSKOV ALEXANDER I ,  KELLEY DOUGLAS P

IPC: G06F1/20

CPC classification number: H05K7/20836 ,  G06F1/20

Abstract: Systems and methods for cooling computer components in large computer systems are disclosed herein. In one embodiment, a computer system configured in accordance with aspects of the invention can include a computer module positioned in a chassis, and an air mover configured to move air through the chassis and past the computer module. The computer system can further include a pressure sensor operably coupled to the air mover. If the pressure sensor determines that the difference between a first air pressure inside the chassis and a second air pressure outside the chassis is less than a preselected pressure, the air mover can increase the flow of air through the chassis and past the computer module.

Abstract translation: 本文公开了用于冷却大型计算机系统中的计算机组件的系统和方法。 在一个实施例中，根据本发明的方面配置的计算机系统可以包括定位在底盘中的计算机模块和构造成使空气移动通过机架并经过计算机模块的空气推动器。 计算机系统还可以包括可操作地联接到空气推进器的压力传感器。 如果压力传感器确定底盘内的第一空气压力与底盘外部的第二空气压力之间的差小于预选压力，则空气推动器可以增加通过底盘并经过计算机模块的空气流。

公开(公告)号：WO2005119410A2

公开(公告)日：2005-12-15

申请号：PCT/US2005/019597

申请日：2005-06-03

Applicant: CRAY INC. ,  HELLRIEGEL, Stephen, V. R. ,  YATSKOV, Alexander, I. ,  KELLEY, Douglas, P.

Inventor： HELLRIEGEL, Stephen, V. R. ,  YATSKOV, Alexander, I. ,  KELLEY, Douglas, P.

IPC: G06F1/20

CPC classification number: H05K7/20836 ,  G06F1/20

Abstract: Systems and methods for cooling computer components in large computer systems are disclosed herein. In one embodiment, a computer system configured in accordance with aspects of the invention can include a computer module positioned in a chassis, and an air mover configured to move air through the chassis and past the computer module. The computer system can further include a pressure sensor operably coupled to the air mover. If the pressure sensor determines that the difference between a first air pressure inside the chassis and a second air pressure outside the chassis is less than a preselected pressure, the air mover can increase the flow of air through the chassis and past the computer module.

Abstract translation: 本文公开了用于冷却大型计算机系统中的计算机组件的系统和方法。 在一个实施例中，根据本发明的方面配置的计算机系统可以包括定位在底盘中的计算机模块和构造成使空气移动通过机架并经过计算机模块的空气推动器。 计算机系统还可以包括可操作地联接到空气推进器的压力传感器。 如果压力传感器确定底盘内的第一空气压力与底盘外部的第二空气压力之间的差小于预选压力，则空气推动器可以增加通过底盘并经过计算机模块的空气流。

公开(公告)号：WO2004104840A3

公开(公告)日：2005-08-25

申请号：PCT/US2004016127

申请日：2004-05-20

Applicant: CRAY INC ,  DIXON R PAUL ,  RESNICK DAVID R ,  SCHWOERER GERALD A ,  MARQUARDT KELLY J ,  GROSSMEIER ALAN M ,  STEINBERGER MICHAEL L ,  SNYDER VAN L ,  BETHARD ROGER A ,  HIGGINS MICHAEL F

Inventor： DIXON R PAUL ,  RESNICK DAVID R ,  SCHWOERER GERALD A ,  MARQUARDT KELLY J ,  GROSSMEIER ALAN M ,  STEINBERGER MICHAEL L ,  SNYDER VAN L ,  BETHARD ROGER A ,  HIGGINS MICHAEL F

IPC: G06F11/10 ,  G06F11/20 ,  G11C29/00 ,  G11C29/44

CPC classification number: G06F11/106 ,  G11C11/401 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/848 ,  G11C2029/0401

Abstract: A memory controller and method that provide a read-refresh (also called "distributed-refresh") mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract translation: 提供读取刷新（也称为“分布式刷新”）操作模式的存储器控​​制器和方法，其中在存储器部件的刷新速率要求内读取存储器的每一行，其中来自不同列的数据 在随后的读取刷新周期中读取行，直到读取每个列地址的所有行，如果找到则擦除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。 为了擦洗，安排了原子读取 - 正确写入操作。 描述了可变优先级的可变定时刷新间隔。 描述了集成卡自测试器和/或卡互换测试器。 描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。