中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.014 seconds)

    SYSTEMS AND METHODS FOR SELECTIVE TUNGSTEN DEPOSITION IN VIAS
    4.
    发明申请
    SYSTEMS AND METHODS FOR SELECTIVE TUNGSTEN DEPOSITION IN VIAS 审中-公开
    VIAS中选择​​性沉积沉积的系统和方法

    公开(公告)号：WO2012047571A3

    公开(公告)日：2012-08-09

    申请号：PCT/US2011053203

    申请日：2011-09-26

    Applicant: NOVELLUS SYSTEMS INC ,  GAO JUWEN ,  JAKKARAJU RAJKUMAR ,  DANEK MICHAL ,  LEI WEI

    Inventor： GAO JUWEN ,  JAKKARAJU RAJKUMAR ,  DANEK MICHAL ,  LEI WEI

    IPC: H01L21/28 ,  H01L21/205 ,  H01L21/31

    CPC classification number: H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

    Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period

    Abstract translation: 一种处理衬底的方法包括提供包括金属层，布置在金属层上的电介质层以及形成在电介质层中的通孔和沟槽中的至少一个的衬底; 在第一沉积周期期间使用化学气相沉积（CVD）沉积金属，其中所述第一沉积周期长于将所述金属沉积在所述金属层上所需的第一成核周期; 在第二成核延迟周期之前停止第一沉积周期，其中需要第二成核周期将金属沉积在电介质层上; 执行存入和停止N次，其中N是大于或等于1的整数; 并且在执行之后，在比第二成核延迟周期长的第二沉积时段期间使用CVD沉积金属

    SYSTEMS AND METHODS FOR SELECTIVE TUNGSTEN DEPOSITION IN VIAS
    5.
    发明申请
    SYSTEMS AND METHODS FOR SELECTIVE TUNGSTEN DEPOSITION IN VIAS 审中-公开
    用于VIAS中选择​​性钨沉积的系统和方法

    公开(公告)号：WO2012047571A2

    公开(公告)日：2012-04-12

    申请号：PCT/US2011/053203

    申请日：2011-09-26

    Applicant: NOVELLUS SYSTEMS INC. ,  GAO, Juwen ,  JAKKARAJU, Rajkumar ,  DANEK, Michal ,  LEI, Wei

    Inventor： GAO, Juwen ,  JAKKARAJU, Rajkumar ,  DANEK, Michal ,  LEI, Wei

    IPC: H01L21/28 ,  H01L21/205 ,  H01L21/31

    CPC classification number: H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

    Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period

    Abstract translation: 用于处理衬底的方法包括：提供衬底，所述衬底包括金属层，布置在所述金属层上的介电层以及形成在所述介电层中的通孔和沟槽中的至少一个; 在第一沉积期期间使用化学气相沉积（CVD）沉积金属，其中第一沉积期长于在金属层上沉积金属所需的第一成核期; 在第二成核延迟时段之前停止第一沉积时段，其中第二成核时段用于将金属沉积在介电层上; 执行N次的存放和停止，其中N为大于或等于1的整数; 并且在执行之后，在比第二成核延迟时段更长的第二沉积时段期间使用CVD沉积金属

    TUNGSTEN FEATURE FILL WITH NUCLEATION INHIBITION
    7.
    发明申请
    TUNGSTEN FEATURE FILL WITH NUCLEATION INHIBITION 审中-公开
    TUNGSTEN功能填充与核心抑制

    公开(公告)号：WO2013148444A1

    公开(公告)日：2013-10-03

    申请号：PCT/US2013/033174

    申请日：2013-03-20

    Applicant: NOVELLUS SYSTEMS, INC. ,  CHANDRASHEKAR, Anand ,  JENG, Esther ,  HUMAYUN, Raashina ,  DANEK, Michal ,  GAO, Juwen ,  WANG, Deqi

    Inventor： CHANDRASHEKAR, Anand ,  JENG, Esther ,  HUMAYUN, Raashina ,  DANEK, Michal ,  GAO, Juwen ,  WANG, Deqi

    IPC: H01L21/31 ,  H01L21/205

    CPC classification number: H01L21/76877 ,  C23C16/045 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/76862 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76898 ,  H01L27/1052 ,  H01L27/10891

    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

    Abstract translation: 这里描述的是用钨填充特征的方法，以及涉及抑制钨成核的相关系统和装置。 在一些实施方案中，所述方法涉及沿特征轮廓的选择性抑制。 选择性地抑制钨成核的方法可以包括将特征暴露于直接或远程等离子体。 在某些实施方案中，可以在选择性抑制期间衬底被偏置。 可以使用包括偏置功率，曝光时间，等离子体功率，工艺压力和等离子体化学在内的工艺参数来调节抑制曲线。 本文描述的方法可用于填充诸如钨通孔的垂直特征，以及诸如垂直NAND（VNAND）字线的水平特征。 这些方法可以用于适形填充和自下而上/内向外填充。 应用实例包括逻辑和存储器触点填充，DRAM掩埋字线填充，垂直集成存储器栅极/字线填充以及使用硅通孔的3-D集成。

Patent Agency Ranking