Abstract:
Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material (212) and subsequently a common gate layer stack is deposited and subsequently patterned.
Abstract:
The present invention allows the formation of sidewall spacers (217,218) adjacent a feature (206) on a substrate (201) without there being an undesirable erosion of the feature. The feature (206) is covered by one or more protective layers (220,207). A layer of a spacer material (211) is deposited over the feature (206) and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers (220, 207) are substantially not affected by the etchant. Thus, the one or more protective layers (220, 207) protect the feature from being exposed to the etchant.
Abstract:
The present invention allows the formation of sidewall spacers (217,218) adjacent a feature (206) on a substrate (201) without there being an undesirable erosion of the feature. The feature (206) is covered by one or more protective layers (220,207). A layer of a spacer material (211) is deposited over the feature (206) and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers (220, 207) are substantially not affected by the etchant. Thus, the one or more protective layers (220, 207) protect the feature from being exposed to the etchant.