公开(公告)号：WO2004097898A2

公开(公告)日：2004-11-11

申请号：PCT/US2004/012709

申请日：2004-04-23

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  LI, Chi Nan Brian ,  HOEFLER, Alexander, B. ,  LIN, Der-Gao

Inventor： LI, Chi Nan Brian ,  HOEFLER, Alexander, B. ,  LIN, Der-Gao

IPC: H01L

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.

Abstract translation: 有源保险丝包括用于形成可变电阻器（106）和选择晶体管（110）的有源熔丝几何形状（120）。 在一个实施例中，有源熔丝几何形状形成在半导体衬底（140）的有源区（160）的一部分中，并且选择栅极（124）设置在有源熔丝几何的端部（123）上方， 形成用于编程有源保险丝的整体选择晶体管（110）。 在有源区域内使用共享的有源保险丝几何形状允许减少面积要求和改进的感测裕度。

公开(公告)号：WO2011136948A3

公开(公告)日：2012-02-02

申请号：PCT/US2011032739

申请日：2011-04-15

Applicant: FREESCALE SEMICONDUCTOR INC ,  HOEFLER ALEXANDER B ,  MOOSA MOHAMED S

Inventor： HOEFLER ALEXANDER B ,  MOOSA MOHAMED S

IPC: G11C17/00 ,  G11C16/34

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A memory system (10) including a one time programmable (OTP) memory (16) is provided. The memory system (10) further includes a write enable verification circuit (14) including an asymmetric inverter stage (30) and a symmetric inverter stage (32) coupled at a node (34). The write enable verification circuit (14) is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node (34) changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node (34) changes at a second rate higher than the first rate. The write enable verification circuit (14) is further configured to generate a verified write enable signal for enabling programming of the OTP memory (16).

Abstract translation: 提供了包括一次可编程（OTP）存储器（16）的存储器系统（10）。 存储器系统（10）还包括写入使能验证电路（14），其包括耦合在节点（34）处的非对称反相器级（30）和对称反相器级（32）。 写使能验证电路（14）被配置为接收写使能信号。 当写使能信号从第一电压电平变为第二电压电平时，节点（34）处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时， 节点（34）处的电压以比第一速率高的第二速率改变。 写使能验证电路（14）还被配置为产生用于实现OTP存储器（16）的编程的经验证的写使能信号。

公开(公告)号：WO2011136948A2

公开(公告)日：2011-11-03

申请号：PCT/US2011/032739

申请日：2011-04-15

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  HOEFLER, Alexander B. ,  MOOSA, Mohamed S.

Inventor： HOEFLER, Alexander B. ,  MOOSA, Mohamed S.

IPC: G11C17/00 ,  G11C16/34

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A memory system (10) including a one time programmable (OTP) memory (16) is provided. The memory system (10) further includes a write enable verification circuit (14) including an asymmetric inverter stage (30) and a symmetric inverter stage (32) coupled at a node (34). The write enable verification circuit (14) is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node (34) changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node (34) changes at a second rate higher than the first rate. The write enable verification circuit (14) is further configured to generate a verified write enable signal for enabling programming of the OTP memory (16).

Abstract translation: 提供了包括一次可编程（OTP）存储器（16）的存储器系统（10）。 存储器系统（10）还包括写入使能验证电路（14），其包括耦合在节点（34）处的非对称反相器级（30）和对称反相器级（32）。 写使能验证电路（14）被配置为接收写使能信号。 当写使能信号从第一电压电平变为第二电压电平时，节点（34）处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时， 节点（34）处的电压以比第一速率高的第二速率改变。 写使能验证电路（14）还被配置为产生用于实现OTP存储器（16）的编程的经验证的写使能信号。

公开(公告)号：WO2008109220A1

公开(公告)日：2008-09-12

申请号：PCT/US2008/053131

申请日：2008-02-06

Applicant: FREESCALE SEMICONDUCTOR INC. ,  HOEFLER, Alexander B.

Inventor： HOEFLER, Alexander B.

IPC: H03K19/177

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: The fuse array (40) described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell (for example, 50 and 60). As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines (70, 72, 74) and bitlines (80, 82, 84) are used to program the fuses (60-68) to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines (70, 72, 74) and bitlines (80, 82, 84) are used to read the fuses (60-68).

Abstract translation: 由于其交叉点架构，本文所述的熔丝阵列（40）非常紧凑并且几乎不使用半导体区域。 所公开的交叉点架构减少必须在每个位单元（例如，50和60）上水平或垂直运行的导体的数量。 结果，每个位单元所需的面积显着减小。 在一个实施例中，使用各种字线（70,72,74）和位线（80,82,84）上的所选择的一组电压来对保险丝（60-68）进行编程以产生具有较紧的阻抗分布的编程保险丝。 类似地，使用各种字线（70,72,74）和位线（80,82,84）上的选定的一组电压来读取保险丝（60-68）。

公开(公告)号：WO2007047165A2

公开(公告)日：2007-04-26

申请号：PCT/US2006/039178

申请日：2006-10-04

Applicant: FREESCALE SEMICONDUCTOR INC. ,  HOEFLER, Alexander B. ,  ORLOWSKI, Marius K.

Inventor： HOEFLER, Alexander B. ,  ORLOWSKI, Marius K.

IPC: H01L21/82

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A programmable fuse (120) and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) (105) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer (107) and a substrate (103). In one example, the conductive layer (107) serves as programmable material, that in a low impedance state, electrically couples conductive structures (119 and 117). A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.

Abstract translation: 一种可编程熔丝（120）和利用硅锗层（SiGe）（例如单晶）（105）作为热绝缘体以形成编程期间产生的热的形成方法。 在一些示例中，可编程熔丝可以在导电层（107）和衬底（103）之间没有任何介电材料。 在一个示例中，导电层（107）用作可编程材料，其在低阻抗状态下电耦合导电结构（119和117）。 将编程电流施加到可编程材料以修改可编程材料以将熔丝置于高阻抗状态。

公开(公告)号：WO2007047165A3

公开(公告)日：2009-04-23

申请号：PCT/US2006039178

申请日：2006-10-04

Applicant: FREESCALE SEMICONDUCTOR INC ,  HOEFLER ALEXANDER B ,  ORLOWSKI MARIUS K

Inventor： HOEFLER ALEXANDER B ,  ORLOWSKI MARIUS K

IPC: H01L27/10

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A programmable fuse (120) and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) (105) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer (107) and a substrate (103). In one example, the conductive layer (107) serves as programmable material, that in a low impedance state, electrically couples conductive structures (119 and 117). A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.

Abstract translation: 一种可编程熔丝（120）和利用硅锗层（SiGe）（例如单晶）（105）作为热绝缘体以形成编程期间产生的热的形成方法。 在一些示例中，可编程熔丝可以在导电层（107）和衬底（103）之间没有任何介电材料。 在一个示例中，导电层（107）用作可编程材料，其在低阻抗状态下电耦合导电结构（119和117）。 将编程电流施加到可编程材料以修改可编程材料以将熔丝置于高阻抗状态。

公开(公告)号：WO2007117790A3

公开(公告)日：2009-03-19

申请号：PCT/US2007063277

申请日：2007-03-05

Applicant: FREESCALE SEMICONDUCTOR INC ,  KENKARE PRASHANT U ,  WALDRIP JEFFREY W ,  HOEFLER ALEXANDER B

Inventor： KENKARE PRASHANT U ,  WALDRIP JEFFREY W ,  HOEFLER ALEXANDER B

IPC: G11C17/18 ,  G11C5/14 ,  G11C7/10 ,  G11C11/34

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A device having an OTP memory (100) is disclosed. A program state of the OTP device (100) is stored at a fuse (106) that is connected in series between a first node (120) and a latch (102). During a program mode, the first node (120) is electrically connected to a program voltage. During a read mode, the first node (120) is electrically connected to ground, whereby a first divided voltage is generated at a first node of the latch.

Abstract translation: 公开了具有OTP存储器（100）的设备。 OTP设备（100）的编程状态被存储在串联连接在第一节点（120）和锁存器（102）之间的熔丝（106）上。 在编程模式期间，第一节点（120）电连接到编程电压。 在读取模式期间，第一节点（120）电连接到地，由此在锁存器的第一节点处产生第一分压。

公开(公告)号：WO2004097898A3

公开(公告)日：2005-01-13

申请号：PCT/US2004012709

申请日：2004-04-23

Applicant: FREESCALE SEMICONDUCTOR INC ,  LI CHI NAN BRIAN ,  HOEFLER ALEXANDER B ,  LIN DER-GAO

Inventor： LI CHI NAN BRIAN ,  HOEFLER ALEXANDER B ,  LIN DER-GAO

IPC: H01L23/525 ,  H01L21/326 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/86

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.

Abstract translation: 有源保险丝包括用于形成可变电阻器（106）和选择晶体管（110）的有源熔丝几何形状（120）。 在一个实施例中，有源熔丝几何形状形成在半导体衬底（140）的有源区（160）的一部分中，并且选择栅极（124）设置在有源熔丝几何的端部（123）上方， 形成用于编程有源保险丝的整体选择晶体管（110）。 在有源区域内使用共享的有源保险丝几何形状允许减少面积要求和改进的感测裕度。

公开(公告)号：WO2007117790A9

公开(公告)日：2008-11-06

申请号：PCT/US2007063277

申请日：2007-03-05

Applicant: FREESCALE SEMICONDUCTOR INC ,  KENKARE PRASHANT U ,  WALDRIP JEFFREY W ,  HOEFLER ALEXANDER B

Inventor： KENKARE PRASHANT U ,  WALDRIP JEFFREY W ,  HOEFLER ALEXANDER B

IPC: G11C17/18

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A device having an OTP memory (100) is disclosed. A program state of the OTP device (100) is stored at a fuse (106) that is connected in series between a first node (120) and a latch (102). During a program mode, the first node (120) is electrically connected to a program voltage. During a read mode, the first node (120) is electrically connected to ground, whereby a first divided voltage is generated at a first node of the latch.

Abstract translation: 公开了具有OTP存储器（100）的设备。 OTP设备（100）的编程状态被存储在串联连接在第一节点（120）和锁存器（102）之间的熔丝（106）上。 在编程模式期间，第一节点（120）电连接到编程电压。 在读取模式期间，第一节点（120）电连接到地，由此在锁存器的第一节点处产生第一分压。

公开(公告)号：WO2006019466A3

公开(公告)日：2007-09-27

申请号：PCT/US2005019506

申请日：2005-06-02

Applicant: FREESCALE SEMICONDUCTOR INC ,  HOEFLER ALEXANDER B ,  QURESHI QADEER A

Inventor： HOEFLER ALEXANDER B ,  QURESHI QADEER A

IPC: G11C7/00

CPC classification number: G11C29/74 ,  G11C7/062 ,  G11C7/14

Abstract: A memory ( 10) not only uses redundant cells (16, 18) but also redundant references (120, 122) to reduce the likelihood of a failure. In one approach a failure in a reference (20, 22) can cause both the primary cell (12, 14) as well as the redundant cell (16, 18) to be ineffective. To overcome this potential problem two references (20, 120) for each bit are employed. In one form, the primary cell (12) of a first bit is compared to one reference (20) and the redundant cell (16) of the first bit is compared to another reference (22). The primary (14) and redundant cell (18) of a second bit can use these two references (20, 22) as well.

Abstract translation: 存储器（10）不仅使用冗余单元（16,18），而且还使用冗余参考（120,122）来减少故障的可能性。 在一种方法中，参考（20,22）中的故障可能导致主要细胞（12,14）以及冗余细胞（16,18）都无效。 为了克服这个潜在问题，采用了每个位的两个参考（20,120）。 在一种形式中，将第一位的主单元（12）与一个参考（20）进行比较，并将第一位的冗余单元（16）与另一个参考（22）进行比较。 第二位的主（14）和冗余单元（18）也可以使用这两个参考（20,22）。