公开(公告)号：WO2022166131A1

公开(公告)日：2022-08-11

申请号：PCT/CN2021/109303

申请日：2021-07-29

申请人： 长鑫存储技术有限公司

发明人： 宫光彩

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L23/528 ,  H01L21/66

摘要： 本公开涉及半导体技术领域，提出了一种半导体结构的熔断填充方法及半导体结构。半导体结构的熔断填充方法包括：提供一半导体结构本体，半导体结构本体内形成有多个熔断器阵列组；熔断熔断器阵列组的互连结构，以在半导体结构本体上形成缺口；在半导体结构本体上形成遮挡层，遮挡层上形成有暴露缺口的通孔；在缺口内形成密封材料层。通过在具有缺口的半导体结构本体上形成遮挡层，且遮挡层上形成有暴露缺口的通孔，即在后续填充缺口时，由于遮挡层的存在不会使得密封材料层大面积地直接覆盖半导体结构本体，避免了后续的清理，且可以保证缺口内可靠地形成密封材料层，以此隔绝外部危险因素的侵入，以此改善半导体结构的使用性能。

公开(公告)号：WO2022061759A1

公开(公告)日：2022-03-31

申请号：PCT/CN2020/117884

申请日：2020-09-25

申请人： 华为技术有限公司

发明人： 陈惠斌 ,  林勇钊 ,  吕镇

IPC分类号： H01L23/525 ,  H01L23/498

摘要： 本申请实施例提供一种基板、封装结构、以及电子设备。所述基板用于与芯片电连接，所述芯片包括功率端子和信号端子，所述基板包括第一基板和安装于所述第一基板的第二基板，所述第一基板包括第一布线，所述第一布线用于与所述功率端子电连接，所述第二基板包括第二布线，述第二布线用于与所述信号端子电连接，所述第二布线的线路之间的间距小于所述第一布线的线路之间的间距。本申请提供的基板尺寸小，集成度高。

公开(公告)号：WO2021203937A1

公开(公告)日：2021-10-14

申请号：PCT/CN2021/081498

申请日：2021-03-18

申请人： 长鑫存储技术有限公司

发明人： 李雄 ,  冯鹏

IPC分类号： H01L23/525

摘要： 一种反熔丝单元结构及反熔丝阵列。所述反熔丝单元结构包括基底、反熔丝器件和选择晶体管。其中所述反熔丝器件形成于所述基底中，包括第一栅极结构、第一源极掺杂区和第一漏极掺杂区，其中所述第一栅极结构与所述第一漏极掺杂区电连接。所述选择晶体管形成于所述基底中，与所述反熔丝器件匹配设置，包括第二栅极结构、第二源极掺杂区和第二漏极掺杂区，其中所述第二漏极掺杂区与所述第一源极掺杂区电连接。

公开(公告)号：WO2021202038A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/020549

申请日：2021-03-02

申请人： MICRON TECHNOLOGY, INC.

发明人： JENSEN, Travis, M. ,  HEMBREE, David, R.

IPC分类号： H01L25/065 ,  H01L23/485 ,  H01L23/525 ,  H01L21/60 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06586 ,  H01L24/02 ,  H01L25/0657 ,  H01L25/50 ,  H01L2924/15311

摘要： Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

公开(公告)号：WO2021173204A1

公开(公告)日：2021-09-02

申请号：PCT/US2020/063310

申请日：2020-12-04

申请人： TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

发明人： BHATTACHERJEE, Arya ,  FULFORD, H. Jim

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L23/532 ,  H01L23/525 ,  H01L23/528 ,  H01L23/00 ,  H01L23/50

摘要： A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. A second interposer substrate is provided and includes a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method further includes joining the first interposer substrate to the second interposer substrate such that the wiring plane is provided as an interface wiring plane between the first and second bulk materials which electrically connects at least one of the first TSVs to at least one of the second TSVs.

公开(公告)号：WO2021096178A1

公开(公告)日：2021-05-20

申请号：PCT/KR2020/015607

申请日：2020-11-09

申请人： 동우 화인켐 주식회사 ,  포항공과대학교 산학협력단

发明人： 최병진 ,  박동필 ,  신승현 ,  홍원빈 ,  박준호

IPC分类号： H01L23/66 ,  H01L23/525 ,  H01L23/485 ,  H01L23/48 ,  H01L23/29 ,  H01Q1/22 ,  H01Q1/38

摘要： 안테나 패키지는 기재, 기재에 결합하는 배선 패턴, 배선 패턴을 밀봉하면서 기재 상에 형성되는 제1 유기 절연막, 제1 유기 절연막 상에 형성되는 안테나 패턴, 제1 유기 절연막을 관통하여 배선 패턴과 안테나 패턴을 연결하는 도전 비아, 및 안테나 패턴을 밀봉하면서 제1 유기 절연막 상에 형성되는 제2 유기 절연막을 포함한다.

公开(公告)号：WO2021061474A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/051117

申请日：2020-09-16

申请人： ILLUMINA, INC.

发明人： EMADI, Arvin ,  ADAY, Jon ,  AGAH, Ali ,  RIVAL, Arnaud

IPC分类号： G01N27/414 ,  H01L21/768 ,  H01L21/683 ,  H01L21/78 ,  H01L21/56 ,  H01L23/525 ,  H01L23/31 ,  H01L23/047

摘要： Provided herein include various examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include obtaining a first carrier bonded to an upper surface of the silicon wafer. This wafer includes through silicon vias (TSVs) extended through openings in a passivation stack, with electrical contacts coupled to portions of the TSVs exposed through these openings. The method may include de-bonding the first carrier from the upper surface of the silicon wafer. The method may include dicing the silicon wafer into subsections comprising dies.

公开(公告)号：WO2021016408A1

公开(公告)日：2021-01-28

申请号：PCT/US2020/043161

申请日：2020-07-23

申请人： KLA CORPORATION

发明人： XIAO, Hong

IPC分类号： H01L23/544 ,  H01L21/66 ,  H01L23/525 ,  H01L23/528

摘要： A device area includes at least a first layer of photoresist and a second layer of photoresist. First layer metrology targets are positioned at an edge of one of the sides of the first layer of the mat. The first layer metrology targets have a relaxed pitch less than a device pitch. Secondary electron and back-scattered electron images can be simultaneously obtained.

公开(公告)号：WO2020263018A1

公开(公告)日：2020-12-30

申请号：PCT/KR2020/008368

申请日：2020-06-26

申请人： 주식회사 아모센스

发明人： 정연수 ,  안주환

IPC分类号： H01L31/12 ,  H01L23/538 ,  H01L23/48 ,  H01L23/367 ,  H01L23/552 ,  H01L23/525 ,  H01L23/528 ,  H01L23/14 ,  H01L25/065

摘要： 전자 소자 어셈블리 패키지, 전자 소자 모듈용 회로 기판 및 이의 제조 방법이 제공된다. 본 발명의 일 실시예에 따른 전자 소자 어셈블리 패키지는 회로 기판; 및 상기 회로 기판 상에 실장되는 전자 소자 및 상기 전자 소자를 구동하는 구동 소자를 포함하며, 상기 회로 기판은, 상기 전자 소자 또는 상기 구동 소자의 전기적 입출력 신호를 전달하거나 상기 전자 소자 또는 상기 구동 소자로부터 발생하는 열을 수집하는 적어도 하나 이상의 비아를 포함하는 배선 층들이 적층된 코어 층; 및 상기 코어 층의 비아와 연결되어 상기 전기적 입출력 신호를 중계하거나 상기 수집된 열을 외부로 방출하는 적어도 하나 이상의 관통 비아를 포함할 수 있다.

公开(公告)号：WO2020197643A1

公开(公告)日：2020-10-01

申请号：PCT/US2020/016773

申请日：2020-02-05

申请人： ADVANCED MICRO DEVICES, INC.

发明人： BHAGAVAT, Milind, S. ,  AGARWAL, Rahul ,  CHENG, Chia-hao

IPC分类号： H01L23/50 ,  H01L23/538 ,  H01L23/525 ,  H01L23/528 ,  H01L25/065 ,  H01L23/31

摘要： Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure (172) having a first plurality of conductor traces (l65d, l65e), a first molding layer (120) on the first RDL structure, plural conductive pillars (205a, 205b) in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure (115) on the first molding layer, the second RDL structure having a second plurality of conductor traces (l65a, 165b), and wherein some of the conductive pillars (205b, 205c) are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.