公开(公告)号：WO2006001915A2

公开(公告)日：2006-01-05

申请号：PCT/US2005016253

申请日：2005-05-11

Applicant: FREESCALE SEMICONDUCTOR INC ,  VENKATESAN SURESH ,  FOISY MARK C ,  MENDICINO MICHAEL A ,  ORLOWSKI MARIUS K

Inventor： VENKATESAN SURESH ,  FOISY MARK C ,  MENDICINO MICHAEL A ,  ORLOWSKI MARIUS K

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L27/1203

Abstract: A semiconductor device structure (10) uses two semiconductor layers (16 & 20) to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors (38) when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors (40) preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers (16 & 20), both the N and P channel transistors (38 & 40) can be optimized for carrier mobility.

Abstract translation: 半导体器件结构（10）使用两个半导体层（16和20）分别优化N沟道晶体管和P沟道晶体管的载流子迁移率。 用于确定它的导电特性是半导体的材料类型，晶面，取向和应变的组合。 当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管（38）的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。 或者，晶面可以是（111），在这种情况下的取向是不重要的。 用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管（40）优选具有拉伸应变，硅半导体材料和（100）平面。 利用分离的半导体层（16和20），N和P沟道晶体管（38和40）都可以针对载流子迁移率进行优化。

公开(公告)号：WO2005117101A2

公开(公告)日：2005-12-08

申请号：PCT/US2005/012391

申请日：2005-04-13

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ORLOWSKI, Marius K. ,  LIU, Chun-Li ,  YEAP, Choh-Fei

Inventor： ORLOWSKI, Marius K. ,  LIU, Chun-Li ,  YEAP, Choh-Fei

IPC: H01L21/8234

CPC classification number: H01L29/0847 ,  H01L29/1033 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78606 ,  H01L29/78639 ,  H01L29/78687

Abstract: Silicon carbon is used as a diffusion barrier (18,108) to germanium so that a silicon layer (20,110) can be subsequently formed without being contaminated with germanium. This is useful in separating silicon layers (20, 110) from silicon germanium layers (16,106) in situations in which both silicon and silicon germanium are desired to be present on the same semiconductor device (10) such as for providing different materials for optimizing carrier mobility between N and P channel transistors (27) and for a raised source/drain (134,136) of silicon in the case of a silicon germanium body.

Abstract translation: 硅碳用作锗的扩散阻挡层（18,108），从而随后可以形成硅层（20,110），而不会被锗污染。 在需要在同一半导体器件（10）上存在硅和硅锗的情况下，例如为了提供用于优化载体的不同材料的情况，这可用于在硅层（20,110）与硅锗层（16,106）之间分离硅层 在硅锗体的情况下，N沟道晶体管（P沟道晶体管）和P沟道晶体管（27）之间的迁移率以及硅的升高的源极/漏极（134,136）的迁移率。

公开(公告)号：WO2005076795A3

公开(公告)日：2005-08-25

申请号：PCT/US2005/001534

申请日：2005-01-12

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ORLOWSKI, Marius, K. ,  ADETUTU, Olumbunmi, O. ,  BARR, Alexander, L.

Inventor： ORLOWSKI, Marius, K. ,  ADETUTU, Olumbunmi, O. ,  BARR, Alexander, L.

IPC: H01L21/36

Abstract: A semiconductor on insulator transistor (45) is formed beginning with a bulk silicon substrate (12). An active region is defined in the substrate (12) and an oxygen-rich silicon layer that is monocrystalline is formed on a top surface of the active region. On this oxygen-rich silicon layer is grown an epitaxial layer of silicon. After formation of the epitaxial layer of silicon, the oxygen-rich silicon layer is converted to silicon oxide (24) while at least a portion of the epitaxial layer remains as monocrystalline silicon. This is achieved by applying high temperature water vapor to the epitaxial layer. The result is a silicon on insulator structure (10) useful for making a transistor (45) in which the gate dielectric (26) is on the remaining monocrystalline silicon, the gate (28) is on the gate dielectric (26), and the channel (36) is in the remaining monocrystalline silicon under the gate (28).

公开(公告)号：WO2005034186A2

公开(公告)日：2005-04-14

申请号：PCT/US2004/029381

申请日：2004-09-10

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ORLOWSKI, Marius, K. ,  BARR, Alexander, L.

Inventor： ORLOWSKI, Marius, K. ,  BARR, Alexander, L.

IPC: H01L

CPC classification number: H01L29/66628 ,  H01L21/76235 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for forming a semiconductor device (10) having isolation structures decreases leakage current. A channel isolation structure (32, 30, 34) decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures (36) are formed under current electrode regions to prevent leakage between the current electrodes (40).

Abstract translation: 用于形成具有隔离结构的半导体器件（10）的方法降低了漏电流。 沟道隔离结构（32,30,34）减小了通过沟道结构的漏电流。 此外，当前电极电介质绝缘结构（36）形成在电流电极区域下，以防止电流电极（40）之间的泄漏。

公开(公告)号：WO2007127523A2

公开(公告)日：2007-11-08

申请号：PCT/US2007/062634

申请日：2007-02-23

Applicant: FREESCALE SEMICONDUCTOR INC. ,  ORLOWSKI, Marius, K.

Inventor： ORLOWSKI, Marius, K.

IPC: H01L29/76

CPC classification number: H01L29/7923 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7887 ,  H01L29/7926

Abstract: A semiconductor device includes a semiconductor structure (105) having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first (615) and second (617) charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode (215) is formed adjacent to the first sidewall. In another embodiment, third (616) and fourth (618) charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.

Abstract translation: 半导体器件包括具有第一侧壁的半导体结构（105）。 沿着第一侧壁在第一电流电极区域和第二电流电极区域之间的半导体结构中形成垂直沟道区域。 第一和第二电荷存储结构形成在电介质层的开口中与第一侧壁相邻。 第一（615）和第二（617）电荷存储结构彼此和半导体结构电隔离。 控制电极（215）与第一侧壁相邻地形成。 在另一个实施例中，第三（616）和第四（618）电荷存储结构可以形成在电介质层的开口中与半导体结构的第二侧壁相邻。

公开(公告)号：WO2007047165A2

公开(公告)日：2007-04-26

申请号：PCT/US2006/039178

申请日：2006-10-04

Applicant: FREESCALE SEMICONDUCTOR INC. ,  HOEFLER, Alexander B. ,  ORLOWSKI, Marius K.

Inventor： HOEFLER, Alexander B. ,  ORLOWSKI, Marius K.

IPC: H01L21/82

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A programmable fuse (120) and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) (105) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer (107) and a substrate (103). In one example, the conductive layer (107) serves as programmable material, that in a low impedance state, electrically couples conductive structures (119 and 117). A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.

Abstract translation: 一种可编程熔丝（120）和利用硅锗层（SiGe）（例如单晶）（105）作为热绝缘体以形成编程期间产生的热的形成方法。 在一些示例中，可编程熔丝可以在导电层（107）和衬底（103）之间没有任何介电材料。 在一个示例中，导电层（107）用作可编程材料，其在低阻抗状态下电耦合导电结构（119和117）。 将编程电流施加到可编程材料以修改可编程材料以将熔丝置于高阻抗状态。

公开(公告)号：WO2006023219A3

公开(公告)日：2006-03-02

申请号：PCT/US2005/026543

申请日：2005-07-27

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ORLOWSKI, Marius, K. ,  VENKATESAN, Suresh

Inventor： ORLOWSKI, Marius, K. ,  VENKATESAN, Suresh

IPC: H01L21/336

Abstract: A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axial stress are both compressive for P-channel transistors and both tensile for N-channel transistors. The result is that carrier mobility is enhanced for both short channel and long channel transistors. Both transistor types can be included on the same integrated circuit.

公开(公告)号：WO2007127523A3

公开(公告)日：2008-07-17

申请号：PCT/US2007062634

申请日：2007-02-23

Applicant: FREESCALE SEMICONDUCTOR INC ,  ORLOWSKI MARIUS K

Inventor： ORLOWSKI MARIUS K

IPC: H01L29/76

CPC classification number: H01L29/7923 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7887 ,  H01L29/7926

Abstract: A semiconductor device includes a semiconductor structure (105) having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first (615) and second (617) charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode (215) is formed adjacent to the first sidewall. In another embodiment, third (616) and fourth (618) charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.

Abstract translation: 半导体器件包括具有第一侧壁的半导体结构（105）。 沿着第一侧壁在第一电流电极区域和第二电流电极区域之间的半导体结构中形成垂直沟道区域。 第一和第二电荷存储结构在电介质层的开口中与第一侧壁相邻形成。 第一（615）和第二（617）电荷存储结构彼此和半导体结构电隔离。 控制电极（215）与第一侧壁相邻地形成。 在另一个实施例中，第三（616）和第四（618）电荷存储结构可以在电介质层的开口中与半导体结构的第二侧壁相邻形成。

公开(公告)号：WO2007127533A3

公开(公告)日：2007-11-08

申请号：PCT/US2007/063966

申请日：2007-03-14

Applicant: FREESCALE SEMICONDUCTOR INC. ,  ORLOWSKI, Marius K.

Inventor： ORLOWSKI, Marius K.

IPC: H01L27/01 ,  H01L21/00

Abstract: A method for forming a semiconductor device includes providing a semiconductor layer (12), forming a passivation layer (20) over the semiconductor layer, wherein the passivation layer has an opening (24) having sidewalls, forming a fin (16) over the semiconductor layer, wherein after forming the passivation layer the fin is within the opening, and forming a portion of a gate within the opening. In one embodiment, a dummy gate (52) is used. In one embodiment, spacers (28, 56) are formed within the opening of the passivation layer. The structure is also discussed.

公开(公告)号：WO2007127533A2

公开(公告)日：2007-11-08

申请号：PCT/US2007063966

申请日：2007-03-14

Applicant: FREESCALE SEMICONDUCTOR INC ,  ORLOWSKI MARIUS K

Inventor： ORLOWSKI MARIUS K

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for forming a semiconductor device includes providing a semiconductor layer (12), forming a passivation layer (20) over the semiconductor layer, wherein the passivation layer has an opening (24) having sidewalls, forming a fin (16) over the semiconductor layer, wherein after forming the passivation layer the fin is within the opening, and forming a portion of a gate within the opening. In one embodiment, a dummy gate (52) is used. In one embodiment, spacers (28, 56) are formed within the opening of the passivation layer. The structure is also discussed.

Abstract translation: 一种用于形成半导体器件的方法包括提供半导体层（12），在所述半导体层上形成钝化层（20），其中所述钝化层具有具有侧壁的开口（24），在所述半导体层上形成鳍状物 层，其中在形成钝化层之后，所述翅片在所述开口内，并且在所述开口内形成门的一部分。 在一个实施例中，使用虚拟门（52）。 在一个实施例中，间隔物（28,56）形成在钝化层的开口内。 还讨论了结构。