公开(公告)号：WO2009115990A3

公开(公告)日：2009-11-12

申请号：PCT/IB2009051132

申请日：2009-03-17

Applicant: NXP BV ,  VAN DER PLOEG HENDRIK ,  JANSSEN ERWIN ,  DORIS KONSTANTINOS

Inventor： VAN DER PLOEG HENDRIK ,  JANSSEN ERWIN ,  DORIS KONSTANTINOS

IPC: H03M1/36

CPC classification number: H03M1/361 ,  H03M1/34

Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21 ) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21 ) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.

Abstract translation: 模数转换器包括用于接收模拟输入信号的信号输入（6）和一组比较器（4）。 每个比较器（4）具有连接到信号输入端（6）的第一输入端（21）和连接到参考电压（16）的第二输入端（22）。 每个比较器基于第一输入端（21）和第二输入端（22）之间的信号比较产生输出。 所有比较器的参考电压相同。 该组比较器（4）对参考电压（16）和输入信号具有不相同的响应，并且是由于内部产生的偏移。 加法器（25）确定比较器组的输出的和，并且转换逻辑（27）根据所确定的和产生输出数字信号。 可以提供多组比较器，每组具有不同的相应参考电压。

公开(公告)号：WO2008149258A3

公开(公告)日：2009-09-24

申请号：PCT/IB2008052079

申请日：2008-05-27

Applicant: NXP BV ,  JANSSEN ERWIN

Inventor： JANSSEN ERWIN

IPC: H03D3/00

CPC classification number: H03D3/006 ,  H03H17/06 ,  H03H2017/0247 ,  H03H2218/04

Abstract: A digital signal processing circuit comprises a band selector (14) for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from the branches. Each branch comprises a sub-sampler (20a,b) for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter (24a,b) with a first FIR filter (32, 34), applied alternatingly to sets of even and to sets of odd samples from the subsampler (20a,b) and a second FIR filter (36, 38) applied to further sets of odd and even samples from the subsampler (20a,b) when the first FIR filter is applied to the even and odd sets respectively. Output samples from the first and second FIR filter (24a,b) are combined to form the branch signals of the branch, according to a changing combination pattern that changes cyclically as a function of sample position and depends on a phase for which the branch is used.

Abstract translation: 数字信号处理电路包括用于从数字采样输入信号的频谱中选择至少一个子带的频带选择器（14）。 带选择器（14）包括对应于各个相位的多个处理分支和用于从分支添加分支信号的加法器（28a，28b）。 每个分支包括用于在与分支相对应的相位处对输入信号的采样值进行子采样的子采样器（20a，b），具有第一FIR滤波器（32,34）的滤波器（24a，b），交替地施加 以及当所述第一FIR滤波器（20a，b）被应用于来自所述二次采样器（20a，b）的另外的奇数和偶数样本集合时，来自所述二次采样器（20a，b）的偶数和一组奇数样本集合和第二FIR滤波器 分别应用于偶数和奇数集。 来自第一和第二FIR滤波器（24a，b）的输出样本被组合以形成分支的分支信号，根据作为样本位置的函数循环变化的变化的组合模式，并且取决于分支是 用过的。

公开(公告)号：WO2006129215A3

公开(公告)日：2006-12-07

申请号：PCT/IB2006/051537

申请日：2006-05-16

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  JANSSEN, Erwin ,  REEFMAN, Derk

Inventor： JANSSEN, Erwin ,  REEFMAN, Derk

IPC: G11B20/10 ,  G11B20/12 ,  G10L19/14 ,  H03M7/00

Abstract: An audio coding scheme allowing PCM signal to lossless DSD signal expansion for next generation optical disc formats. The method of encoding an input DSD signal includes up-sampling a corresponding PCM signal to the DSD sample rate. Then a set of loop filter parameters for a noise-shaping loop of a sigma-delta modulator are generated, either using a random starting condition of the sigma-delta modulator or including synchronization parameters. This will allow a decoder to regenerate an almost perfect signal, but still it needs a correction signal to be able to bit identically regenerate the DSD input signal. Therefore, a correction signal is generated based on a difference between a sigma- delta modulated version of the up-sampled PCM signal and the input DSD signal, wherein the sigma-delta modulated version of the up-sampled PCM signal is obtained using the set of loop filter parameters. The correction signal may be adapted to be applied to the low bit PCM signal, to the up-sampled PCM signal or to the output bit stream. Finally, an expansion bit stream is generated where an encoded version of the set of loop filter parameters and an encoded version of the correction signal are included. The decoder can reproduce the original DSD signal based on the already available PCM signal and the described expansion bit stream. Thus, the coding scheme enables top quality audio with minimal storage overhead since the already available PCM signal is used in combination with an expansion bit stream. Since only an additional data stream is required to be stored on a disc, e.g. as part of an MPEG stream, DSD functionality is added to existing systems without causing compatibility problems.

公开(公告)号：WO2009081326A1

公开(公告)日：2009-07-02

申请号：PCT/IB2008/055311

申请日：2008-12-15

Applicant: NXP B.V. ,  BREKELMANS, Johannes, H., A. ,  JANSSEN, Erwin ,  DORIS, Konstantinos ,  PHILIPPE, Pascal

Inventor： BREKELMANS, Johannes, H., A. ,  JANSSEN, Erwin ,  DORIS, Konstantinos ,  PHILIPPE, Pascal

IPC: H04L7/00 ,  H04L27/233

CPC classification number: H04L27/2332 ,  H04L27/2338

Abstract: A device for receiving an RF input signal (2) and for processing the received RF input signal (2) is provided. The device comprises: an input (3) receiving the RF input signal (2); a clock circuit (34) generating a reference clock signal having a clock circuit specific reference frequency (fclock); and a frequency feedback control loop (17, 18, 20, 21, 22, 23; 35, 37, 38). The frequency feedback control loop is adapted to extract frequency information from the RF input signal (2), to put the clock circuit specific reference frequency (fclock) into relation with the extracted frequency information and to correct for inaccuracies of the clock circuit specific reference frequency based on this relation.

Abstract translation: 提供了一种用于接收RF输入信号（2）并用于处理所接收的RF输入信号（2）的装置。 该装置包括：接收RF输入信号的输入端（3）; 产生具有时钟电路特定参考频率（fclock）的参考时钟信号的时钟电路（34）; 和频率反馈控制回路（17,18,20,21,22,23; 35,37,38）。 频率反馈控制环路适于从RF输入信号（2）提取频率信息，将时钟电路特定参考频率（fclock）与提取的频率信息相关联，并校正时钟电路特定参考频率的不准确性 基于这种关系。

公开(公告)号：WO2009069066A1

公开(公告)日：2009-06-04

申请号：PCT/IB2008/054927

申请日：2008-11-24

Applicant: NXP B.V. ,  BREKELMANS, Johannes, H., A. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

Inventor： BREKELMANS, Johannes, H., A. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/12

CPC classification number: H04B1/12

Abstract: A device for receiving a RF signal (1) is provided. The device comprises an input (3) receiving a RF input signal (2); an analog pre-processing circuitry (11) pre- processing the RF input signal (2); an analog-digitalconverter (8) converting the pre- processed RF input signal to a digital signal (9); and a digital signal processing unit (10) digitallyprocessing the digital signal (9). The digital signal processing unit (10) is adapted to compensate signaldistortions introduced by the analog pre-processing circuitry (11).

Abstract translation: 提供一种用于接收RF信号（1）的设备。 该装置包括接收RF输入信号（2）的输入端（3）。 预处理RF输入信号（2）的模拟预处理电路（11）; 将预处理的RF输入信号转换为数字信号（9）的模数转换器（8）; 以及对所述数字信号（9）进行数字处理的数字信号处理单元（10）。 数字信号处理单元（10）适于补偿由模拟预处理电路（11）引入的信号失真。

公开(公告)号：WO2006129215A2

公开(公告)日：2006-12-07

申请号：PCT/IB2006051537

申请日：2006-05-16

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  JANSSEN ERWIN ,  REEFMAN DERK

Inventor： JANSSEN ERWIN ,  REEFMAN DERK

IPC: G11B20/10 ,  G10L19/16 ,  G11B20/12 ,  H03M7/00

CPC classification number: H03M7/3006 ,  G10L19/167 ,  G11B20/10481 ,  G11B20/10527 ,  G11B20/1262 ,  G11B2020/00014 ,  G11B2020/00065 ,  G11B2020/10546 ,  G11B2020/1288 ,  G11B2220/2541 ,  G11B2220/2579 ,  H03M7/3028

Abstract: An audio coding scheme allowing PCM signal to lossless DSD signal expansion for next generation optical disc formats. The method of encoding an input DSD signal includes up-sampling a corresponding PCM signal to the DSD sample rate. Then a set of loop filter parameters for a noise-shaping loop of a sigma-delta modulator are generated, either using a random starting condition of the sigma-delta modulator or including synchronization parameters. This will allow a decoder to regenerate an almost perfect signal, but still it needs a correction signal to be able to bit identically regenerate the DSD input signal. Therefore, a correction signal is generated based on a difference between a sigma- delta modulated version of the up-sampled PCM signal and the input DSD signal, wherein the sigma-delta modulated version of the up-sampled PCM signal is obtained using the set of loop filter parameters. The correction signal may be adapted to be applied to the low bit PCM signal, to the up-sampled PCM signal or to the output bit stream. Finally, an expansion bit stream is generated where an encoded version of the set of loop filter parameters and an encoded version of the correction signal are included. The decoder can reproduce the original DSD signal based on the already available PCM signal and the described expansion bit stream. Thus, the coding scheme enables top quality audio with minimal storage overhead since the already available PCM signal is used in combination with an expansion bit stream. Since only an additional data stream is required to be stored on a disc, e.g. as part of an MPEG stream, DSD functionality is added to existing systems without causing compatibility problems.

Abstract translation: 音频编码方案允许PCM信号用于下一代光盘格式的无损DSD信号扩展。 编码输入DSD信号的方法包括将相应的PCM信号上采样到DSD采样率。 然后，使用Σ-Δ调制器的随机起始条件或包括同步参数来生成Σ-Δ调制器的噪声整形环路的一组环路滤波器参数。 这将允许解码器再生几乎完美的信号，但是仍然需要一个校正信号以能够相同地重新生成DSD输入信号。 因此，基于上采样PCM信号的Σ-Δ调制版本与输入DSD信号之间的差产生校正信号，其中上采样PCM信号的Σ-Δ调制版本使用该集合 的环路滤波器参数。 校正信号可适用于低比特PCM信号，上采样PCM信号或输出比特流。 最后，生成扩展位流，其中包括一组环路滤波器参数的编码版本和校正信号的编码版本。 解码器可以基于已经可用的PCM信号和所描述的扩展位流再现原始DSD信号。 因此，由于已经可用的PCM信号与扩展位流结合使用，所以编码方案实现了具有最小存储开销的顶级质量音频。 由于只需要额外的数据流来存储在盘上，例如， 作为MPEG流的一部分，DSD功能被添加到现有系统中，而不会引起兼容性问题。

公开(公告)号：WO2004093316A3

公开(公告)日：2005-01-27

申请号：PCT/IB2004050452

申请日：2004-04-15

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  JANSSEN ERWIN ,  REEFMAN DERK

Inventor： JANSSEN ERWIN ,  REEFMAN DERK

IPC: H03H17/02 ,  H03H21/00

CPC classification number: H03H17/0294 ,  H03H2017/0295

Abstract: An adaptive filtering device and method where at least one adaptive filter receives an input signal and a metering device receives an output of the at least one adaptive filter, monitors a characteristic of the output, such as power of high-frequency components, and forwards a correction signal in a feedback loop to adjust the characteristic of the at least one filter in order to change the characteristic of the output. An adaptive filtering device (200) and method where two low-pass FIR filters (202, 204) receive an input signal, a weighted adder (206) receives outputs from the two low-pass FIR filters and changes a weighting of each to produce filtered output data, and a controller (208) that receives a cut­off frequency (203), supplies the cut-off frequency to the two low-pass FIR filters, and supplies a signal to the weighted adder for varying the weighting of each of the low-pass FIR filters to switch therebetween.

Abstract translation: 一种自适应滤波装置和方法，其中至少一个自适应滤波器接收输入信号，并且计量装置接收所述至少一个自适应滤波器的输出，监视输出的特性，例如高频分量的功率，并转发 校正信号，以调整至少一个滤波器的特性，以改变输出的特性。 一种自适应滤波装置（200）和方法，其中两个低通FIR滤波器（202,204）接收输入信号，加权加法器（206）接收来自两个低通FIR滤波器的输出并改变每个低通FIR滤波器的加权以产生 滤波后的输出数据和接收截止频率（203）的控制器（208）将截止频率提供给两个低通FIR滤波器，并将信号提供给加权加法器，以改变每个 低通FIR滤波器在其间切换。

公开(公告)号：WO2004030221A1

公开(公告)日：2004-04-08

申请号：PCT/IB2003/003656

申请日：2003-08-08

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  REEFMAN, Derk ,  JANSSEN, Erwin

Inventor： REEFMAN, Derk ,  JANSSEN, Erwin

IPC: H03M3/02

CPC classification number: H03M3/394 ,  H03M3/43

Abstract: Sigma-delta modulation is provided, wherein an input signal is feeded to at least two parallel filters, a first one of the filters preferably being a lower order filter and a second one of the filters preferably being a higher order filter, wherein output of the filters are weighted and wherein the weighted output from the at least two filters is quantized, in order to enable a sigma-delta modulation with variable order.

Abstract translation: 提供了Σ-Δ调制，其中输入信号被馈送到至少两个并行滤波器，滤波器中的第一滤波器优选地是低阶滤波器，并且滤波器中的第二滤波器优选地是高阶滤波器，其中输出信号 滤波器被加权，并且其中来自至少两个滤波器的加权输出被量化，以便能够以可变顺序进行Σ-Δ调制。

公开(公告)号：WO2010055475A1

公开(公告)日：2010-05-20

申请号：PCT/IB2009/055017

申请日：2009-11-12

Applicant: NXP B.V. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

Inventor： DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/00 ,  H03H17/02 ,  H04N5/44

CPC classification number: H04B1/001 ,  H03H17/06 ,  H03H2218/08 ,  H04B1/0025

Abstract: A multi-channel receiver comprising an ADC and a multi-band, multi-channel selector. The ADC converts a broad-band multi-channel signal into a digital signal. The digital signal is then broken into sub-bands each containing a plurality of channels. A channel selector selects desired channels from the appropriate sub-band. The multi-channel receiver may deliver simultaneous channels equal to the number of channel selectors that have been implemented. The multi-channel receiver may be implemented on a single integrated circuit.

Abstract translation: 一种包括ADC和多频道多通道选择器的多声道接收机。 ADC将宽带多通道信号转换为数字信号。 然后将数字信号分成各自包含多个信道的子带。 信道选择器从适当的子带选择所需信道。 多信道接收机可以提供等于已经实现的信道选择器的数量的同时信道。 多通道接收器可以在单个集成电路上实现。

公开(公告)号：WO2009098641A1

公开(公告)日：2009-08-13

申请号：PCT/IB2009/050439

申请日：2009-02-03

Applicant: NXP B.V. ,  SCHOLTENS, Peter, C., S. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

Inventor： SCHOLTENS, Peter, C., S. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H03M1/06

CPC classification number: H03M1/0602 ,  H03M1/1014 ,  H03M1/1215

Abstract: A time-interleaved signal converter (800) comprising a plurality of analogue-to- digital converters (ADCO-3), hereinafter termed ADCs, the ADCs being configured to sample an input signal at a common sampling rate and at differing phases to produce a corresponding plurality of digital signal outputs, the signal converter (800) being configured to produce a combined digital signal output from a combination of the plurality of digital signal outputs, wherein the signal converter (800) is configured to determine a sampling timing error (ΔT) between a pair of the ADCs by comparing an autocorrelation (710) of the combined digital signal output with a cross-correlation (720) of a respective pair of the plurality of digital signal outputs.

Abstract translation: 包括多个模数转换器（ADCO-3）（以下称为ADC）的时间交织信号转换器（800），所述ADC被配置为以公共采样率和不同阶段对输入信号进行采样以产生 相应的多个数字信号输出，所述信号转换器（800）被配置为产生从所述多个数字信号输出的组合输出的组合数字信号，其中所述信号转换器（800）被配置为确定采样定时误差 T），通过将组合数字信号输出的自相关（710）与相应的多个数字信号输出对的互相关（720）进行比较来实现。