公开(公告)号：WO2009081326A1

公开(公告)日：2009-07-02

申请号：PCT/IB2008/055311

申请日：2008-12-15

Applicant: NXP B.V. ,  BREKELMANS, Johannes, H., A. ,  JANSSEN, Erwin ,  DORIS, Konstantinos ,  PHILIPPE, Pascal

Inventor： BREKELMANS, Johannes, H., A. ,  JANSSEN, Erwin ,  DORIS, Konstantinos ,  PHILIPPE, Pascal

IPC: H04L7/00 ,  H04L27/233

CPC classification number: H04L27/2332 ,  H04L27/2338

Abstract: A device for receiving an RF input signal (2) and for processing the received RF input signal (2) is provided. The device comprises: an input (3) receiving the RF input signal (2); a clock circuit (34) generating a reference clock signal having a clock circuit specific reference frequency (fclock); and a frequency feedback control loop (17, 18, 20, 21, 22, 23; 35, 37, 38). The frequency feedback control loop is adapted to extract frequency information from the RF input signal (2), to put the clock circuit specific reference frequency (fclock) into relation with the extracted frequency information and to correct for inaccuracies of the clock circuit specific reference frequency based on this relation.

Abstract translation: 提供了一种用于接收RF输入信号（2）并用于处理所接收的RF输入信号（2）的装置。 该装置包括：接收RF输入信号的输入端（3）; 产生具有时钟电路特定参考频率（fclock）的参考时钟信号的时钟电路（34）; 和频率反馈控制回路（17,18,20,21,22,23; 35,37,38）。 频率反馈控制环路适于从RF输入信号（2）提取频率信息，将时钟电路特定参考频率（fclock）与提取的频率信息相关联，并校正时钟电路特定参考频率的不准确性 基于这种关系。

公开(公告)号：WO2009069066A1

公开(公告)日：2009-06-04

申请号：PCT/IB2008/054927

申请日：2008-11-24

Applicant: NXP B.V. ,  BREKELMANS, Johannes, H., A. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

Inventor： BREKELMANS, Johannes, H., A. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/12

CPC classification number: H04B1/12

Abstract: A device for receiving a RF signal (1) is provided. The device comprises an input (3) receiving a RF input signal (2); an analog pre-processing circuitry (11) pre- processing the RF input signal (2); an analog-digitalconverter (8) converting the pre- processed RF input signal to a digital signal (9); and a digital signal processing unit (10) digitallyprocessing the digital signal (9). The digital signal processing unit (10) is adapted to compensate signaldistortions introduced by the analog pre-processing circuitry (11).

Abstract translation: 提供一种用于接收RF信号（1）的设备。 该装置包括接收RF输入信号（2）的输入端（3）。 预处理RF输入信号（2）的模拟预处理电路（11）; 将预处理的RF输入信号转换为数字信号（9）的模数转换器（8）; 以及对所述数字信号（9）进行数字处理的数字信号处理单元（10）。 数字信号处理单元（10）适于补偿由模拟预处理电路（11）引入的信号失真。

公开(公告)号：WO2010044000A1

公开(公告)日：2010-04-22

申请号：PCT/IB2009/054346

申请日：2009-10-05

Applicant: NXP B.V. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

Inventor： DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H03M1/06 ,  H03M1/46

CPC classification number: H03M1/0614 ,  H03M1/1215 ,  H03M1/466

Abstract: This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit. In another embodiment the DAC signal is routed through a separate second buffer circuit. By use of a single buffer circuit, or where there is ideal matching of the buffer circuits in the latter embodiment, the distortion effects are completely eliminated; however, for practical imperfectly matched buffer circuits according to the latter embodiment, the gain and off-set mismatches can be accommodated through calibration of the buffers or, in suitable applications, through the DAC calibration.

Abstract translation: 本发明涉及模数转换器（ADC），尤其涉及时间交错ADC和连续近似寄存器（SAR）ADC。 在采用SAR ADC单位的常规时间交错ADC中，输入信号通过跟踪保持电路（T / H），然后通过缓冲电路在SAR ADC单元之前进行处理。 在这里，通过比较器将信号与来自SAR逻辑的数模转换器（DAC）信号进行比较。 缓冲器减小了电容负载和物理布局设计对SAR ADC输入的影响，但通常具有非线性响应，从而对输入信号引入失真。 这可能会限制ADC的线性度，特别是对于使用低电源电压运行的高速ADC。 本发明的目的是减少或消除缓冲器非线性的影响。 这在一些实施例中通过将信号通过相同的缓冲器电路路由到比较器来完成。 在另一个实施例中，DAC信号被路由通过单独的第二缓冲电路。 通过使用单个缓冲电路，或者在后面的实施例中存在缓冲电路的理想匹配的情况下，失真效应被完全消除; 然而，对于根据后一实施例的实际不完全匹配的缓冲器电路，增益和偏移不匹配可以通过缓冲器的校准或者在适当的应用中通过DAC校准来适应。

公开(公告)号：WO2009115990A2

公开(公告)日：2009-09-24

申请号：PCT/IB2009/051132

申请日：2009-03-17

Applicant: NXP B.V. ,  VAN DER PLOEG, Hendrik ,  JANSSEN, Erwin ,  DORIS, Konstantinos

Inventor： VAN DER PLOEG, Hendrik ,  JANSSEN, Erwin ,  DORIS, Konstantinos

CPC classification number: H03M1/361 ,  H03M1/34

Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21 ) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21 ) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.

Abstract translation: 模数转换器包括用于接收模拟输入信号的信号输入端（6）和一组比较器（4）。 每个比较器（4）具有连接到信号输入端（6）的第一输入端（21）和连接到参考电压（16）的第二输入端（22）。 每个比较器基于第一输入（21）和第二输入（22）处的信号的比较来生成输出。 所有比较器的参考电压都相同。 该组比较器（4）对参考电压（16）和输入信号具有不同的响应，并且是由于内部产生的偏移。 加法器（25）确定该组比较器的输出之和，并且转换逻辑（27）根据所确定的总和产生输出数字信号。 可以提供多套比较器，每套具有不同的参考电压。

公开(公告)号：WO2009069065A1

公开(公告)日：2009-06-04

申请号：PCT/IB2008/054926

申请日：2008-11-24

Applicant: NXP B.V. ,  BREKELMANS, Johannes, H., A. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

Inventor： BREKELMANS, Johannes, H., A. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/12 ,  H04B1/18 ,  H04N5/775

CPC classification number: H04B1/12 ,  H04B1/18

Abstract: A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog- digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).

Abstract translation: 提供了一种用于接收具有环通输出（16）的RF信号（1; 21）的装置。 该装置包括：接收RF输入信号的输入端（3）; 将所述RF输入信号（2）转换成数字信号（9）的模拟数字转换器（8）; 数字信号处理单元（10）数字处理数字信号（9）; 将经处理的数字信号（13）转换成对应于RF输入信号（2）的环通RF信号（15）的数模转换器（14）; 以及输出环通RF信号（15）的环路输出（16）。

公开(公告)号：WO2010055475A1

公开(公告)日：2010-05-20

申请号：PCT/IB2009/055017

申请日：2009-11-12

Applicant: NXP B.V. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

Inventor： DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/00 ,  H03H17/02 ,  H04N5/44

CPC classification number: H04B1/001 ,  H03H17/06 ,  H03H2218/08 ,  H04B1/0025

Abstract: A multi-channel receiver comprising an ADC and a multi-band, multi-channel selector. The ADC converts a broad-band multi-channel signal into a digital signal. The digital signal is then broken into sub-bands each containing a plurality of channels. A channel selector selects desired channels from the appropriate sub-band. The multi-channel receiver may deliver simultaneous channels equal to the number of channel selectors that have been implemented. The multi-channel receiver may be implemented on a single integrated circuit.

Abstract translation: 一种包括ADC和多频道多通道选择器的多声道接收机。 ADC将宽带多通道信号转换为数字信号。 然后将数字信号分成各自包含多个信道的子带。 信道选择器从适当的子带选择所需信道。 多信道接收机可以提供等于已经实现的信道选择器的数量的同时信道。 多通道接收器可以在单个集成电路上实现。

公开(公告)号：WO2009098641A1

公开(公告)日：2009-08-13

申请号：PCT/IB2009/050439

申请日：2009-02-03

Applicant: NXP B.V. ,  SCHOLTENS, Peter, C., S. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

Inventor： SCHOLTENS, Peter, C., S. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H03M1/06

CPC classification number: H03M1/0602 ,  H03M1/1014 ,  H03M1/1215

Abstract: A time-interleaved signal converter (800) comprising a plurality of analogue-to- digital converters (ADCO-3), hereinafter termed ADCs, the ADCs being configured to sample an input signal at a common sampling rate and at differing phases to produce a corresponding plurality of digital signal outputs, the signal converter (800) being configured to produce a combined digital signal output from a combination of the plurality of digital signal outputs, wherein the signal converter (800) is configured to determine a sampling timing error (ΔT) between a pair of the ADCs by comparing an autocorrelation (710) of the combined digital signal output with a cross-correlation (720) of a respective pair of the plurality of digital signal outputs.

Abstract translation: 包括多个模数转换器（ADCO-3）（以下称为ADC）的时间交织信号转换器（800），所述ADC被配置为以公共采样率和不同阶段对输入信号进行采样以产生 相应的多个数字信号输出，所述信号转换器（800）被配置为产生从所述多个数字信号输出的组合输出的组合数字信号，其中所述信号转换器（800）被配置为确定采样定时误差 T），通过将组合数字信号输出的自相关（710）与相应的多个数字信号输出对的互相关（720）进行比较来实现。

公开(公告)号：WO2009090514A1

公开(公告)日：2009-07-23

申请号：PCT/IB2008/055560

申请日：2008-12-29

Applicant: NXP B.V. ,  DORIS, Konstantinos ,  VAN DER PLOEG, Hendrik ,  JANSSEN, Erwin

Inventor： DORIS, Konstantinos ,  VAN DER PLOEG, Hendrik ,  JANSSEN, Erwin

IPC: H03M1/12

CPC classification number: H03M1/1215

Abstract: The invention discloses an analog-to-digital converter circuit and an associated method. The analog-to-digital converter circuit comprises a main signal input (51) for inputting an analog signal into the circuit, a front-end circuitry (1), and a back-end circuitry (2). The front-end circuitry (1) comprises a plurality (N) of sampling units (52 1 ,...,52 N ), each having a signal input (52*) and a signal output (52**), wherein the signal input (52*) of each of the sampling units (52 1 ,...,52 N ) is connected to said main signal input (51), and wherein said main signal input (51) is configured to feed the analog signal to said plurality of sampling units (52 1 ,...,52 N ) using time interleaving. The back-end circuitry (2) comprises a plurality of demultiplexers (57 1 ,...,57 N ), each having a signal input (57*) and a group (K) of signal outputs (57 1 **,...,57 K **), wherein the signal output (52**) of each sampling unit (52 1 ,...,52 N ) is connected to the signal input (57*) of one demultiplexer of said plurality of demultiplexers (57 1 ,...,57 N ); and further comprises a plurality (N) of groups (K) of ADC units (53 1 ,...,53 K ), each ADC unit having a signal input (53*) and a data output (53**), wherein the signal outputs (57 1 **,...,57 K **) of each demultiplexer (57 1 ,...,57 N ) are connected to the signal inputs (53*) of the ADC units (53 1 ,...,53 K ) of one group of ADC units (53 1 ,...,53 K ), and wherein said demultiplexers (57 1 ,...,57 N ) are configured to feed the sampled signal to said plurality of groups of ADC units (53 1 ,...,53 K ) using time interleaving.

Abstract translation: 本发明公开了一种模拟 - 数字转换器电路及其相关方法。 模数转换器电路包括用于将模拟信号输入电路的主信号输入端（51），前端电路（1）和后端电路（2）。 前端电路（1）包括多个（N）个采样单元（521，...，52N），每个采样单元具有信号输入（52 *）和信号输出（52 **），其中信号输入 每个采样单元（521，...，52N）的每个采样单元（52 *）连接到所述主信号输入端（51），其中所述主信号输入端（51）被配置为将模拟信号馈送到所述多个 采样单元（521，...，52N）。 后端电路（2）包括多个解复用器（571，...，57N），每个解复用器具有信号输入（57 *）和信号输出（571 **，...， 57K **），其中每个采样单元（521，...，52N）的信号输出（52 **）连接到所述多个解复用器（571，...）中的一个解复用器的信号输入端（57 *）。 。，57N）; 并且还包括多个（N）组（K）的ADC单元（531，...，53K），每个ADC单元具有信号输入（53 *）和数据输出（53 **），其中所述信号 每个解复用器（571，...，57N）的输出（571 **，...，57K **）连接到ADC单元（531，...，53K）的信号输入（53 *） 一组ADC单元（531，...，53K），并且其中所述解复用器（571，...，57N）被配置为将采样信号馈送到所述多组ADC单元（531，...，57N） 53K）使用时间交织。

公开(公告)号：WO2008114205A2

公开(公告)日：2008-09-25

申请号：PCT/IB2008/051000

申请日：2008-03-17

Applicant: NXP B.V. ,  DEN BESTEN, Gerrit, W. ,  JANSSEN, Erwin

Inventor： DEN BESTEN, Gerrit, W. ,  JANSSEN, Erwin

IPC: H04L7/00 ,  G06F1/32 ,  H03L7/10

CPC classification number: H04L7/0004 ,  H03L7/0891 ,  H03L7/189 ,  H04L7/0008 ,  H04L7/0091 ,  H04L7/0338

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract translation: 数据通信系统具有带第一时钟发生电路的发射器和带第二时钟发生电路的接收器。 在连续的数据突发之间至少有一个特定的时钟发生电路断电。 该系统在特定时钟发生电路断电时加快系统操作使用的启动。 系统在启动时以预定值预设特定时钟发生电路的操作量。

公开(公告)号：WO2008149258A2

公开(公告)日：2008-12-11

申请号：PCT/IB2008/052079

申请日：2008-05-27

Applicant: NXP B.V. ,  JANSSEN, Erwin

Inventor： JANSSEN, Erwin

IPC: H03D7/00

CPC classification number: H03D3/006 ,  H03H17/06 ,  H03H2017/0247 ,  H03H2218/04

Abstract: A digital signal processing circuit comprises a band selector (14) for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector (14) comprises a plurality of processing branches corresponding to respective phases and an adder (28a, 28b) for adding branch signals from the branches. Each branch comprises a sub-sampler (20a,b) for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter (24a,b) with a first FIR filter (32, 34), applied alternatingly to sets of even and to sets of odd samples from the subsampler (20a,b) and a second FIR filter (36, 38) applied to further sets of odd and even samples from the subsampler (20a,b) when the first FIR filter is applied to the even and odd sets respectively. Output samples from the first and second FIR filter (24a,b) are combined to form the branch signals of the branch, according to a changing combination pattern that changes cyclically as a function of sample position and depends on a phase for which the branch is used.

Abstract translation: 数字信号处理电路包括用于从数字采样输入信号的频谱中选择至少一个子带的频带选择器（14）。 带选择器（14）包括对应于各个相位的多个处理分支和用于从分支添加分支信号的加法器（28a，28b）。 每个分支包括用于在与分支相对应的相位处对输入信号的采样值进行子采样的子采样器（20a，b），具有第一FIR滤波器（32,34）的滤波器（24a，b），交替地施加 以及当所述第一FIR滤波器（20a，b）被应用于来自所述二次采样器（20a，b）的另外的奇数和偶数样本集合时，来自所述二次采样器（20a，b）的偶数和一组奇数样本集合和第二FIR滤波器 分别应用于偶数和奇数集。 来自第一和第二FIR滤波器（24a，b）的输出样本被组合以形成分支的分支信号，根据作为样本位置的函数循环变化的变化的组合模式，并且取决于分支是 用过的。