摘要:
Luftfahrzeug-Türanordnung, insbesondere für ein Flugzeug, umfassend eine Tür; einen Türrahmen; einen Traglenker mit einer türseitigen Schwenkachse (AD), an der die Tür schwenkbar gelagert ist, und einer rahmenseitigen Schwenkachse (AF), an welcher der Traglenker (8) schwenkbar am Türrahmen gelagert ist, wobei zumindest die türseitige Schwenkachse (AD) durch zwei in Höhenrichtung (Y) des Traglenkers (8) voneinander beabstandete Gelenke (G1, G2) definiert ist, von denen mindestens eines (G1; G2) zwei in Höhenrichtung (Y) voneinander beabstandete Lagerstellen (L1a, L1b) besitzt; einen am türseitigen Bereich des Traglenkers (8) angeordneten Schwenkantrieb (10) zum Verschwenken der Tür; und ein Abtriebselement (12; 14, 16), welches mit dem Schwenkantrieb (10) und der Tür gekoppelt ist und eine Stellbewegung des Schwenkantriebs (10) auf die Tür überträgt. Die Luftfahrzeug-Türanordnung ist dadurch gekennzeichnet, dass eine (L1b) der zwei Lagerstellen (L1a, L1b) von mindestens einem (G1) der rahmenseitigen Gelenke (G1, G2) als ein Schwenkantrieb-Lagerbeschlag (34) ausgebildet ist (L1B), an dem der Schwenkantrieb (10) befestigt ist.
摘要:
An interleave address generating circuit of a multicore type turbo decode processing apparatus of the present invention includes intermediate value generating blocks whose arithmetic portions are modified so as to generate not only an interleave address corresponding to the forward direction but also an interleave address corresponding to the backward direction. By using initial parameters which are preliminarily decomposed into parameters for a memory bank and physical addresses, the intermediate value generating blocks having a restricted bit width in two parallel are disposed in two parallel and the two intermediate value generating blocks are connected to each other through signal lines for exchanging carry signals.
摘要:
In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.
摘要:
In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.