公开(公告)号：WO2012102940A1

公开(公告)日：2012-08-02

申请号：PCT/US2012/021942

申请日：2012-01-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ABOU-KHALIL, Michael, J. ,  GAUTHIER, Robert, J. Jr. ,  LEE, Tom, C. ,  LI, Junjun ,  SOUVICK, Mitra ,  PUTNAM, Christopher, S.

Inventor： ABOU-KHALIL, Michael, J. ,  GAUTHIER, Robert, J. Jr. ,  LEE, Tom, C. ,  LI, Junjun ,  SOUVICK, Mitra ,  PUTNAM, Christopher, S.

IPC: G06F17/50

CPC classification number: H01L27/0255 ,  G06F17/5022 ,  G06F17/5045 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/6609 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/861

Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode (56). The device structure includes one or more dielectric regions (20a, 20b, 20c), such as STI regions, positioned in the device region (18) and intersecting the p-n junction (52, 54) between an anode (40, 42) and cathode (28, 30, 48a, 48b, 49a, 49b, 50a, 50b). The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

Abstract translation: 在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及用于横向二极管（56）的设计结构。 器件结构包括位于器件区域（18）中并与pn结（52,54）相交的阳极（40,42）和阴极之间的一个或多个电介质区域（20a，20b，20c），例如STI区域 （28,30,48a，48b，49a，49b，50a，50b）。 可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。 介质区域的宽度差和存在产生不对称二极管结构。 由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。

公开(公告)号：WO2005086183A1

公开(公告)日：2005-09-15

申请号：PCT/US2004/003148

申请日：2004-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHEN, Fen ,  CHRISTIANSEN, Cathryn, J. ,  DUFRESNE, Roger, A. ,  LEE, Tom, C. ,  LI, Baozhen ,  STRONG, Alvin, W. ,  WATSON, Kimball, M. ,  WYNNE, Jean, E.

Inventor： CHEN, Fen ,  CHRISTIANSEN, Cathryn, J. ,  DUFRESNE, Roger, A. ,  LEE, Tom, C. ,  LI, Baozhen ,  STRONG, Alvin, W. ,  WATSON, Kimball, M. ,  WYNNE, Jean, E.

IPC: H01C17/22

CPC classification number: H01C17/22

Abstract: A method (300) for trimming resistors (422), and an apparatus (400) for trimming resistors are provided for resistors made of a material whose resistance changes in response to applied voltage. The method comprises measuring (310) the resistance of the resistor. The measured resistance is compared (320) with a target resistance. Based. on the difference (330) between the measured resistance and the target resistance, trimming (340) control parameters (maximum sweep voltage, sweep rate, pulse voltage level, pulse duration, pulse shape) of the applied voltage are calculated. An electric power corresponding to the calculated trimming control parameters is applied across the resistor so as to cause the resistor's resistance to approach the target resistance. The resistor's resistance is measured again and compared with the target resistance. If the difference is not sufficiently small, process described above is repeated until the difference between the measured resistance and the target resistance is less than a pre-specified value.

Abstract translation: 提供了一种用于微调电阻器（422）的方法（300）和用于微调电阻器的装置（400），用于由其电阻响应于施加电压而改变的材料制成的电阻器。 该方法包括测量（310）电阻器的电阻。 将测得的电阻与目标电阻进行比较（320）。 根据。 在测量电阻和目标电阻之间的差（330）上，计算施加电压的修整（340）控制参数（最大扫描电压，扫描速率，脉冲电压电平，脉冲持续时间，脉冲形状）。 对应于计算的微调控制参数的电力施加在电阻器两端，以使电阻器的电阻接近目标电阻。 再次测量电阻的电阻，并与目标电阻进行比较。 如果差异不够小，则重复上述处理，直到测得的电阻和目标电阻之间的差小于预定值。

公开(公告)号：WO2011002612A3

公开(公告)日：2011-03-10

申请号：PCT/US2010038934

申请日：2010-06-17

Applicant: IBM ,  ABOU-KHALIL MICHEL J ,  LEE TOM C ,  LI JUNJUN ,  GAUTHIER ROBERT J JR ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK

Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  LI JUNJUN ,  GAUTHIER ROBERT J JR ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK

IPC: H01L21/82 ,  H01L27/02

CPC classification number: G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract translation: 公开了电子熔丝编程/重新编程电路的实施例。 在一个实施例中，电子熔丝（150）具有两个短的高原子扩散电阻导体层（110,130），其位于长的低原子扩散电阻导体（110,130）的相对侧（121,122）上和同一端（123） 层（120）。 使用电压源（170）来改变施加到端子（第一端= 170/161/110;第二端= 170/162/130;第三端= 170/163 / 以控制导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内电子的双向流动，从而形成开路和/或短路 在长导体层 - 短导体层界面（125,126）处。 这种开路和/或短路的形成可以用来实现不同的编程状态（11,01,10,00）。 其他电路结构实施例将e熔丝（650）与额外的导体层和额外的端子结合，以允许更多的编程状态。 还公开了相关联的电子熔丝编程和重新编程方法的实施例。

公开(公告)号：WO2009117255A3

公开(公告)日：2009-12-30

申请号：PCT/US2009036091

申请日：2009-03-05

Applicant: IBM ,  CHAPPLE-SOKOL JONATHAN D ,  DELIBAC DANIEL A ,  ZHONG-XIANG HE ,  LEE TOM C ,  MURPHY WILLIAM J ,  SULLIVAN TIMOTHY D ,  THOMAS DAVID C ,  VANSLETTE DANIEL S

Inventor： CHAPPLE-SOKOL JONATHAN D ,  DELIBAC DANIEL A ,  ZHONG-XIANG HE ,  LEE TOM C ,  MURPHY WILLIAM J ,  SULLIVAN TIMOTHY D ,  THOMAS DAVID C ,  VANSLETTE DANIEL S

IPC: H01L21/4763

CPC classification number: H01L23/53223 ,  H01L23/5329 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack (360L, Figure 5) comprising, from bottom to top, a low-oxygen-reactivity metal layer (10), a bottom transition metal layer (20), a bottom transition metal nitride layer (30), an aluminum-copper layer (40), an optional top transition metal layer (50), and a top transition metal nitride layer (60). The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen- reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

Abstract translation: 在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。 从底部到顶部包含低氧反应性金属层（10），底部过渡金属层（20），底部过渡金属氮化物层（30），铝合金（30）的金属层堆叠（360L，图5） （40），可选的顶部过渡金属层（50）和顶部过渡金属氮化物层（60）。 金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。 低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和介电材料层之间的化合物的形成，从而提高了至少一种铝基金属线的电迁移率 不与介电材料层相互作用。

公开(公告)号：WO2009117255A2

公开(公告)日：2009-09-24

申请号：PCT/US2009/036091

申请日：2009-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHAPPLE-SOKOL, Jonathan, D. ,  DELIBAC, Daniel, A. ,  ZHONG-XIANG, He ,  LEE, Tom, C. ,  MURPHY, William, J. ,  SULLIVAN, Timothy, D. ,  THOMAS, David, C. ,  VANSLETTE, Daniel, S.

Inventor： CHAPPLE-SOKOL, Jonathan, D. ,  DELIBAC, Daniel, A. ,  ZHONG-XIANG, He ,  LEE, Tom, C. ,  MURPHY, William, J. ,  SULLIVAN, Timothy, D. ,  THOMAS, David, C. ,  VANSLETTE, Daniel, S.

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53223 ,  H01L23/5329 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack (360L, Figure 5) comprising, from bottom to top, a low-oxygen-reactivity metal layer (10), a bottom transition metal layer (20), a bottom transition metal nitride layer (30), an aluminum-copper layer (40), an optional top transition metal layer (50), and a top transition metal nitride layer (60). The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen- reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

Abstract translation: 包含嵌入在电介质材料层中的下面的W通孔的底层互连层形成在半导体衬底上。 从底部到顶部包括低氧反应性金属层（10），底部过渡金属层（20），底部过渡金属氮化物层（30），铝 - 铜层（40），可选的顶部过渡金属层（50）和顶部过渡金属氮化物层（60）。 将金属层叠层光刻图案化以形成至少一个构成金属互连结构的铝基金属线。 低氧反应性金属层增强了至少一个铝基金属线的电迁移抗性，因为低氧反应性金属层防止了底部过渡金属层和电介质材料层之间的化合物的形成， 不与介电材料层相互作用。

公开(公告)号：WO2012047464A1

公开(公告)日：2012-04-12

申请号：PCT/US2011/051500

申请日：2011-09-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ABOU-KHALIL, Michel ,  GAUTHIER, Robert, J. ,  LEE, Tom, C. ,  LI, Junjun ,  MITRA, Souvick ,  PUTNAM, Christopher, S.

Inventor： ABOU-KHALIL, Michel ,  GAUTHIER, Robert, J. ,  LEE, Tom, C. ,  LI, Junjun ,  MITRA, Souvick ,  PUTNAM, Christopher, S.

IPC: H01L27/04 ,  H01L23/60

CPC classification number: H01L27/0262 ,  H01L29/747 ,  H01L29/87 ,  H02H9/04

Abstract: Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode (10a) of a first of the back-to-back stacked SCR (10) is connected to an input (30). An anode (20a) of a second of the back-to-back stacked SCR (20) is connected to ground (GND). Cathodes (10b, 20b) of the first and second of the back- to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes (Di, D2) directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes (D3, D4) of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

Abstract translation: 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背层叠SCR（10）中的第一个的阳极（10a）连接到输入（30）。 背对背层叠SCR（20）中的第二个的阳极（20a）连接到地（GND）。 第一和第二背对背层叠SCR的阴极（10b，20b）连接在一起。 对称双向背对背SCR中的每一个包括一对二极管（Di，D2），其将电流引向阴极，其在施加电压时变为反向偏置，从而有效地将激活元件从对称双向 背对背SCR，而另一个对称双向背对背SCR的二极管（D3，D4）在与反向偏置二极管相同的方向上引导电流。

公开(公告)号：WO2011002612A2

公开(公告)日：2011-01-06

申请号：PCT/US2010/038934

申请日：2010-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ABOU-KHALIL, Michel, J. ,  LEE, Tom, C. ,  LI, Junjun ,  GAUTHIER, Robert, J., Jr. ,  PUTNAM, Christopher, S. ,  MITRA, Souvick

Inventor： ABOU-KHALIL, Michel, J. ,  LEE, Tom, C. ,  LI, Junjun ,  GAUTHIER, Robert, J., Jr. ,  PUTNAM, Christopher, S. ,  MITRA, Souvick

IPC: H01L21/82 ,  H01L27/02

CPC classification number: G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract translation: 公开了电子熔丝编程/重新编程电路的实施例。 在一个实施例中，电熔丝（150）具有位于长低原子扩散电阻导体的相对侧（121,122）和同一端（123）上的两个短的高原子扩散电阻导体层（110,130） 层（120）。 使用电压源（170）来改变极性，并且可选地改变施加到端子的电压的大小（第一端子= 170/161/110;第二端子= 170/162/130;第三端子= 170/163 / 导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内的电子的双向流动，从而形成开口和/或短路 在长导体层 - 短导体层界面（125,126）处。 这种打开和/或短路的形成可用于实现不同的编程状态（11，01，10，00）。 其他电路结构实施例包括具有附加导体层的电子熔丝（650）和附加端子，以便允许甚至更多的编程状态。 还公开了相关联的电熔丝编程和重新编程方法的实施例。

公开(公告)号：WO2005048304A3

公开(公告)日：2005-07-28

申请号：PCT/US2004036660

申请日：2004-11-04

Applicant: IBM ,  BADAMI DINESH A ,  LEE TOM C ,  LI BAOZHEN ,  MATUSIEWICZ GERALD ,  MOTSIFF WILLIAM T ,  MUZZY CHRISTOPHER D ,  WATSON KIMBALL M ,  WYNNE JEAN E

Inventor： BADAMI DINESH A ,  LEE TOM C ,  LI BAOZHEN ,  MATUSIEWICZ GERALD ,  MOTSIFF WILLIAM T ,  MUZZY CHRISTOPHER D ,  WATSON KIMBALL M ,  WYNNE JEAN E

IPC: H01L23/525 ,  H01L27/10 ,  H01L23/58 ,  H01L29/00

CPC classification number: H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract translation: 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的第一介电层。 熔丝连接在第一电介质层的顶部。 熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方，直接穿过两个通孔。 两个台面各自包括第三自钝化导电材料。 激光熔丝通过将激光束引导到熔丝链来编程。 控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。 这种电阻变化被检测并转换成数字信号。

公开(公告)号：WO2005048304A2

公开(公告)日：2005-05-26

申请号：PCT/US2004/036660

申请日：2004-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BADAMI, Dinesh, A. ,  LEE, Tom, C. ,  LI, Baozhen ,  MATUSIEWICZ, Gerald ,  MOTSIFF, William, T. ,  MUZZY, Christopher, D. ,  WATSON, Kimball, M. ,  WYNNE, Jean, E.

Inventor： BADAMI, Dinesh, A. ,  LEE, Tom, C. ,  LI, Baozhen ,  MATUSIEWICZ, Gerald ,  MOTSIFF, William, T. ,  MUZZY, Christopher, D. ,  WATSON, Kimball, M. ,  WYNNE, Jean, E.

IPC: H01L

CPC classification number: H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract translation: 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的第一介电层。 熔丝链接在第一介电层的顶部上。 熔丝链路电连接两个通孔并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方并直接位于两个过孔上方。 两个台面均包括第三自钝化导电材料。 激光熔丝通过将激光束引导至熔丝链路进行编程。 控制激光束使得响应于激光束对熔丝链路的影响，熔丝链路的电阻改变但熔丝链路不被熔断。 这种电阻变化被感测并转换成数字信号。