公开(公告)号：WO2014124271A1

公开(公告)日：2014-08-14

申请号：PCT/US2014/015319

申请日：2014-02-07

Applicant: SUBRAMANIAN, Chitra K. ,  LIN, Halbert S. ,  ALAM, Syed M. ,  ANDRE, Thomas ,  EVERSPIN TECHNOLOGIES, INC.

Inventor： SUBRAMANIAN, Chitra K. ,  LIN, Halbert S. ,  ALAM, Syed M. ,  ANDRE, Thomas

IPC: G06F11/00

CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements.

Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。

公开(公告)号：WO2014058994A3

公开(公告)日：2014-07-24

申请号：PCT/US2013064088

申请日：2013-10-09

Applicant: THOMAS ANDRE ,  ALAM SYED M ,  LIN HALBERT S ,  EVERSPIN TECHNOLOGIES INC

Inventor： ANDRE THOMAS ,  ALAM SYED M ,  LIN HALBERT S

IPC: G11C7/00 ,  G11C11/4076

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到预充电命令和响应于接收到激活命令的与激活命令有关的第二系列事件，存储器设备执行与预充电命令有关的第一系列事件。 存储设备延迟第二系列事件的开始，直到第一系列事件完成。

公开(公告)号：WO2014058994A2

公开(公告)日：2014-04-17

申请号：PCT/US2013/064088

申请日：2013-10-09

Applicant: ANDRE, Thomas ,  ALAM, Syed M. ,  LIN, Halbert S. ,  EVERSPIN TECHNOLOGIES, INC.

Inventor： ANDRE, Thomas ,  ALAM, Syed M. ,  LIN, Halbert S.

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。