公开(公告)号：WO2007120159A2

公开(公告)日：2007-10-25

申请号：PCT/US2006/023123

申请日：2006-06-13

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ANDRE, Thomas W. ,  SUBRAMANIAN, Chitra K.

Inventor： ANDRE, Thomas W. ,  SUBRAMANIAN, Chitra K.

IPC: H01L21/336

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: An antifuse circuit (10) provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse (18) has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier (12) provides the resistance state signal. A plurality of reference magnetic tunnel junctions (16) are coupled in parallel and to the sense amplifier (12), each (50, 52, 54) having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier (12) to differ from each resistance state of the MTJ antifuse (18). A write circuit selectively provides a current sufficient to create the program voltage when the write circuit (20) is enabled to program the antifuse magnetic tunnel junction (18). Upon detecting a change in resistance in the MTJ antifuse (18), the write circuit (20) reduces current supplied to the antifuse (18). Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.

Abstract translation: 反熔丝电路（10）以每比特为基础提供一个信号，该信号指示MTJ（磁性隧道结）反熔丝（18）是否已被预先编程为响应于编程电压的低电阻状态。 读出放大器（12）提供电阻状态信号。 多个参考磁隧道结（16）并联耦合到读出放大器（12），每个（50,52,54）具有在一个范围内的电阻以提供可由感测放大器确定的集合电阻 （12）与MTJ反熔丝（18）的每个电阻状态不同。 当写入电路（20）能够编程反熔丝磁性隧道结（18）时，写入电路选择性地提供足以产生编程电压的电流。 当检测到MTJ反熔丝（18）中的电阻变化时，写入电路（20）减少提供给反熔丝（18）的电流。 多个反熔丝可以同时编程。 调整晶体管的栅极氧化物厚度以获得最佳性能。

公开(公告)号：WO2010074904A1

公开(公告)日：2010-07-01

申请号：PCT/US2009/066405

申请日：2009-12-02

Applicant: EVERSPIN TECHNOLOGIES, INC. ,  NAHAS, Joseph, J. ,  ANDRE, Thomas, W. ,  SUBRAMANIAN, Chitra, K.

Inventor： NAHAS, Joseph, J. ,  ANDRE, Thomas, W. ,  SUBRAMANIAN, Chitra, K.

IPC: G11C11/00

CPC classification number: G11C7/04 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673

Abstract: A random access memory architecture includes a first series connected pair of memory elements (202, 206, 302, 306, 402, 404) having a first resistance and a second series connected pair of memory elements (204, 208, 304, 308, 406, 408) having a second resistance coupled in parallel with the first series connected pair of memory elements, wherein a current flows in the first direction through both of the first and second series connected pair of memory elements. A sense amplifier (14) is coupled to an array (16) of MRAM cells (77), each including a memory element, and includes a voltage bias portion (12), the voltage bias portion including the first and second series connected pair of memory elements. The memory elements may be, for example, magnetic tunnel junctions.

Abstract translation: 随机存取存储器架构包括具有第一电阻和第二串联连接的存储器元件对（204,208,304,308,406）的第一串联连接的存储器元件对（202,206,302,306,402,404） ，408），其具有与所述第一串联连接的存储器元件并联耦合的第二电阻，其中电流沿所述第一和第二串联连接的一对存储器元件沿所述第一方向流动。 感测放大器（14）耦合到MRAM单元（77）的阵列（16），每个阵列（16）包括存储元件，并且包括电压偏置部分（12），所述电压偏置部分包括第一和第二串联连接对 记忆元素 存储元件可以是例如磁性隧道结。

公开(公告)号：WO2007120159A3

公开(公告)日：2009-04-16

申请号：PCT/US2006023123

申请日：2006-06-13

Applicant: FREESCALE SEMICONDUCTOR INC ,  ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K

Inventor： ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K

IPC: G11C17/00 ,  G11C7/02 ,  G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C17/02 ,  G11C17/18

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: An antifuse circuit (10) provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse (18) has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier (12) provides the resistance state signal. A plurality of reference magnetic tunnel junctions (16) are coupled in parallel and to the sense amplifier (12), each (50, 52, 54) having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier (12) to differ from each resistance state of the MTJ antifuse (18). A write circuit selectively provides a current sufficient to create the program voltage when the write circuit (20) is enabled to program the antifuse magnetic tunnel junction (18). Upon detecting a change in resistance in the MTJ antifuse (18), the write circuit (20) reduces current supplied to the antifuse (18). Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.

Abstract translation: 反熔丝电路（10）以每比特为基础提供一个信号，该信号指示MTJ（磁性隧道结）反熔丝（18）是否已被预先编程为响应于编程电压的低电阻状态。 读出放大器（12）提供电阻状态信号。 多个参考磁隧道结（16）并联耦合到读出放大器（12），每个（50,52,54）具有在一个范围内的电阻以提供可由感测放大器确定的集合电阻 （12）与MTJ反熔丝（18）的每个电阻状态不同。 当写入电路（20）能够编程反熔丝磁性隧道结（18）时，写入电路选择性地提供足以产生编程电压的电流。 当检测到MTJ反熔丝（18）中的电阻变化时，写入电路（20）减少提供给反熔丝（18）的电流。 多个反熔丝可以同时编程。 调整晶体管的栅极氧化物厚度以获得最佳性能。

公开(公告)号：WO2005027135A1

公开(公告)日：2005-03-24

申请号：PCT/US2004/022510

申请日：2004-07-15

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  NAHAS, Joseph, J. ,  ANDRE, Thomas, W. ,  SUBRAMANIAN, Chitra, K. ,  LIN, Halbert

Inventor： NAHAS, Joseph, J. ,  ANDRE, Thomas, W. ,  SUBRAMANIAN, Chitra, K. ,  LIN, Halbert

IPC: G11C11/00

CPC classification number: G11C11/1695 ,  G11C11/1675

Abstract: A write driver (36) uses a reference current (102) that is reflected to a driver circuit (114) by a voltage. The driver circuit (114) is sized in relation to the device (104) that provides the voltage so that the current through the driver (114) is a predetermined multiple of the reference current (102). This voltage is coupled to the driver circuit (114) through a switch (110). The switch (110) is controlled so that the driver circuit (114) only receives the voltage when the write line (52) is to have write current through it as determined by a decoder (22) responsive to an address. The driver (114) is affirmatively disabled when the write line (52) is intended to not have current passing through it. As an enhancement to overcome ground bounce due to high currents, the input to the driver can be capacitively coupled (120) to the ground terminal that experiences such bounce. Additional enhancements provide benefits in amplitude and edge rate control.

Abstract translation: 写驱动器（36）使用被电压反射到驱动电路（114）的参考电流（102）。 驱动器电路（114）的尺寸相对于提供电压的装置（104）的尺寸，使得通过驱动器（114）的电流是参考电流（102）的预定倍数。 该电压通过开关（110）耦合到驱动器电路（114）。 控制开关（110）使得当写入线（52）响应于地址由解码器（22）确定时，驱动器电路（114）仅接收电压。 当写入线（52）旨在不具有通过它的电流时，驱动器（114）被肯定地禁用。 作为克服由于高电流引起的地面反弹的增强，驱动器的输入可以电容耦合（120）到经历这种反弹的接地端子。 附加的增强功能可以提供幅度和边缘速率控制的优点。

公开(公告)号：WO2014124271A1

公开(公告)日：2014-08-14

申请号：PCT/US2014/015319

申请日：2014-02-07

Applicant: SUBRAMANIAN, Chitra K. ,  LIN, Halbert S. ,  ALAM, Syed M. ,  ANDRE, Thomas ,  EVERSPIN TECHNOLOGIES, INC.

Inventor： SUBRAMANIAN, Chitra K. ,  LIN, Halbert S. ,  ALAM, Syed M. ,  ANDRE, Thomas

IPC: G06F11/00

CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements.

Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。

公开(公告)号：WO2007001855A3

公开(公告)日：2007-05-31

申请号：PCT/US2006023121

申请日：2006-06-13

Applicant: FREESCALE SEMICONDUCTOR INC ,  ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K

Inventor： ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K

IPC: H01L21/336

CPC classification number: G11C17/18 ,  G11C11/1673 ,  G11C11/1695 ,  G11C11/5692 ,  G11C17/02

Abstract: A patterned polysilicon gate (18) is over a metal layer (16) that is over a gate dielectric layer (14), which in turn is over a semiconductor substrate (12). A thin layer (20) of material is conformally deposited over the polysilicon gate (18) and the exposed metal layer (16) and then etched back to form a sidewall spacer (22) on the polysilicon gate (18) and to re-expose the previously exposed portion of the metal layer (16). The re-exposed metal layer (16) is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer (22). Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate (18) but for the protection provided by the sidewall spacer (22). After the re-exposed metal (16) has been removed, a transistor is formed in which the metal layer (14,24) sets the work function of the gate of the transistor.

Abstract translation: 图案化多晶硅栅极（18）位于栅极电介质层（14）之上的金属层（16）的上方，栅极电介质层又在半导体衬底（12）上。 材料的薄层（20）共形沉积在多晶硅栅极（18）和暴露的金属层（16）上，然后被回蚀刻以在多晶硅栅极（18）上形成侧壁间隔物（22）并重新暴露 金属层（16）的先前曝光的部分。 使用对栅极介电材料和侧壁间隔物（22）选择性的蚀刻剂来蚀刻再曝光的金属层（16）。 尽管这种蚀刻基本上是各向异性的，但是它具有各向同性的成分，其蚀刻多晶硅栅极（18）的侧壁，但是用于由侧壁间隔物（22）提供的保护。 在再暴露的金属（16）已经被去除之后，形成晶体管，其中金属层（14,24）设置晶体管的栅极的功函数。

公开(公告)号：WO2006083402A3

公开(公告)日：2007-03-01

申请号：PCT/US2005045205

申请日：2005-12-14

Applicant: FREESCALE SEMICONDUCTOR INC ,  NAHAS JOSEPH J ,  ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K

Inventor： NAHAS JOSEPH J ,  ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K

IPC: H03M13/00 ,  G11C29/00

CPC classification number: G11C7/22 ,  G11C11/16 ,  G11C2207/2263

Abstract: A controller (105) for a toggle memory that performs burst writes by reading a group of bits in the toggle memory (103) and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.

Abstract translation: 一种用于触发存储器的控制器（105），其通过读取所述触发存储器（103）中的一组位来执行突发写入，并将所述脉冲串的每个接收的数据字与所述组的一部分进行比较，以确定哪个单元被切换以进入 突发写入在切换存储器中的数据。 在一个示例中，触发存储器包括具有使用多个自由磁性层的单元的磁阻随机存取存储器（MRAM），当经历沿两个方向的一系列磁脉冲时，该状态之间切换状态。 因为对脉冲串的一组数据执行一次读取，所以执行突发写入所需的时间减少。

公开(公告)号：WO2007001855A2

公开(公告)日：2007-01-04

申请号：PCT/US2006/023121

申请日：2006-06-13

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ANDRE, Thomas W. ,  SUBRAMANIAN, Chitra K.

Inventor： ANDRE, Thomas W. ,  SUBRAMANIAN, Chitra K.

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C11/1673 ,  G11C11/1695 ,  G11C11/5692 ,  G11C17/02

Abstract: A patterned polysilicon gate (18) is over a metal layer (16) that is over a gate dielectric layer (14), which in turn is over a semiconductor substrate (12). A thin layer (20) of material is conformally deposited over the polysilicon gate (18) and the exposed metal layer (16) and then etched back to form a sidewall spacer (22) on the polysilicon gate (18) and to re-expose the previously exposed portion of the metal layer (16). The re-exposed metal layer (16) is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer (22). Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate (18) but for the protection provided by the sidewall spacer (22). After the re-exposed metal (16) has been removed, a transistor is formed in which the metal layer (14,24) sets the work function of the gate of the transistor.

Abstract translation: 图案化多晶硅栅极（18）位于栅极电介质层（14）上的金属层（16）上方，该栅极电介质层（14）又位于半导体衬底（12）上方。 在多晶硅栅极（18）和暴露的金属层（16）上共形地沉积材料薄层（20），然后回蚀刻以在多晶硅栅极（18）上形成侧壁间隔物（22）并重新曝光 之前暴露的金属层（16）部分。 使用对栅极电介质材料和侧壁间隔物（22）有选择性的蚀刻剂来蚀刻重新暴露的金属层（16）。 尽管这种蚀刻基本上是各向异性的，但它具有各向同性的成分，其将蚀刻多晶硅栅极（18）的侧壁，但是用于由侧壁间隔物（22）提供的保护。 在重新暴露的金属（16）已经被去除之后，形成晶体管，其中金属层（14,24）设置晶体管的栅极的功函数。

公开(公告)号：WO2006083402A2

公开(公告)日：2006-08-10

申请号：PCT/US2005/045205

申请日：2005-12-14

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  NAHAS, Joseph J. ,  ANDRE, Thomas W. ,  SUBRAMANIAN, Chitra K.

Inventor： NAHAS, Joseph J. ,  ANDRE, Thomas W. ,  SUBRAMANIAN, Chitra K.

IPC: G11C29/00

CPC classification number: G11C7/22 ,  G11C11/16 ,  G11C2207/2263

Abstract: A controller (105) for a toggle memory that performs burst writes by reading a group of bits in the toggle memory (103) and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.

Abstract translation: 一种用于触发存储器的控制器（105），其通过读取所述触发存储器（103）中的一组位来执行突发写入，并将所述脉冲串的每个接收的数据字与所述组的一部分进行比较，以确定哪个单元被切换以进入 突发写入在切换存储器中的数据。 在一个示例中，触发存储器包括具有使用多个自由磁性层的单元的磁阻随机存取存储器（MRAM），当经历沿两个方向的一系列磁脉冲时，该状态之间切换状态。 因为对脉冲串的一组数据执行一次读取，所以执行突发写入所需的时间减少。