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    MAGNETORESISTIVE STACK DEVICE FABRICATION METHODS
    1.
    发明申请
    MAGNETORESISTIVE STACK DEVICE FABRICATION METHODS 审中-公开

    公开(公告)号：WO2020041582A1

    公开(公告)日：2020-02-27

    申请号：PCT/US2019/047693

    申请日：2019-08-22

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： SUN, Jijun

    IPC: H01L43/12 ,  H01F10/30

    Abstract: Fabrication of a magnetoresistive device, comprising a magnetically fixed region (40) on at least one seed region (20, 25) on an electrically conductive region (15), involves forming a seed region (20'; 21), treating the seed region by exposing a surface thereof to a gas, such as oxygen, and optionally forming a second seed region (22) thereon. Alternatively, a gas, such as oxygen or nitrogen, or one or more atomic elements, such as boron or carbon, may be added during (sputter) deposition of the seed region (25).

    METHODS FOR MANUFACTURING MAGNETORESISTIVE STACK DEVICES
    2.
    发明申请
    METHODS FOR MANUFACTURING MAGNETORESISTIVE STACK DEVICES 审中-公开

    公开(公告)号：WO2020041546A1

    公开(公告)日：2020-02-27

    申请号：PCT/US2019/047619

    申请日：2019-08-22

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： AGGARWAL, Sanjeev ,  DESHPANDE, Sarin ,  NAGEL, Kerry ,  KARRE, Santosh

    IPC: H01L43/12

    Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.

    DELAYED WRITE-BACK IN MEMORY
    6.
    发明申请
    DELAYED WRITE-BACK IN MEMORY 审中-公开
    在存储器中延迟回写

    公开(公告)号：WO2017189065A1

    公开(公告)日：2017-11-02

    申请号：PCT/US2017/015637

    申请日：2017-01-30

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： ANDRE, Thomas ,  ALAM, Syed M. ,  SUBRAMANIAN, Chitra ,  BARKATULLAH, Javed S.

    IPC: G11C11/16 ,  G11C7/22 ,  G11C7/10 ,  G11C16/32

    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

    Abstract translation: 具有延迟回写到对应于先前打开的页面的数据阵列的存储器允许避免与回写操作相关联的延迟。 在初始激活打开第一页并且该页的读取/写入操作完成之后，打开页面回写到存储器单元阵列被延迟直到完成后续激活操作（打开新页面）之后。 还公开了在没有另一个激活操作的情况下强制回写的技术。

    SHORT DETECTION AND INVERSION
    7.
    发明申请
    SHORT DETECTION AND INVERSION 审中-公开
    短期检测和反转

    公开(公告)号：WO2016053985A1

    公开(公告)日：2016-04-07

    申请号：PCT/US2015/052855

    申请日：2015-09-29

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： ANDRE, Thomas ,  SLAUGHTER, Jon ,  HOUSSAMEDDINE, Dimitri ,  ALAM, Syed, M.

    IPC: G06F11/10

    CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

    Abstract translation: 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。

    ECC WORD CONFIGURATION FOR SYSTEM-LEVEL ECC COMPATIBILITY
    8.
    发明申请
    ECC WORD CONFIGURATION FOR SYSTEM-LEVEL ECC COMPATIBILITY 审中-公开
    ECC字配置系统级ECC兼容性

    公开(公告)号：WO2016049418A1

    公开(公告)日：2016-03-31

    申请号：PCT/US2015/052151

    申请日：2015-09-25

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： ALAM, Syed, M. ,  ANDRE, Thomas

    IPC: G06F11/10

    CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1076

    Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be perform. ed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.

    Abstract translation: 在一些示例中，存储器设备包括被配置为存储组织成多个ECC字的数据页的存储器阵列。 存储装置还包括用于与页面相关联的每个ECC字的至少一个输入/输出焊盘，使得存储器装置可以在与页面和第二级相关联的每个ECC字上执行第一级错误校正 的纠错可能会执行。 在特定时间段内由每个输入/输出焊盘输出的数据。 存储器件的一个或多个输入/输出焊盘中的每一个可被配置为在从外部源访问期间仅向外部源提供每个ECC字的一位数据。

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