公开(公告)号：WO2009111257A2

公开(公告)日：2009-09-11

申请号：PCT/US2009/035230

申请日：2009-02-26

Applicant: ADVANTECH GLOBAL, LTD ,  BRODY, Thomas, Peter ,  MARCANIO, Joseph, A.

Inventor： BRODY, Thomas, Peter

IPC: G05F3/16

CPC classification number: C23C14/042 ,  C23C14/562 ,  H01L27/1288 ,  H01L27/14683

Abstract: In a method of reducing or undoing progressive threshold shift in a thin-film-transistor (TFT) circuit, first and second voltages applied to source and gate terminals of a first transistor cause the first transistor to conduct and apply the first voltage to the gate terminal of the second transistor. The first voltage applied to the gate terminal of the second transistor coacts with a reference voltage coupled to the source terminal of the second transistor via an LED element to cause the second transistor to not conduct whereupon the LED element does not receive electrical power. After a first predetermined period of time sufficient to reduce or undo a progressive threshold shift in the second transistor, the application of the first voltage to the gate terminal of the second transistor is terminated.v t stabilization of tfts in oled backplanes

Abstract translation: 在减薄或消除薄膜晶体管（TFT）电路中逐行阈值偏移的方法中，施加到第一晶体管的源极和栅极端子的第一和第二电压使得第一晶体管导通并将第一电压施加到栅极 端子。 施加到第二晶体管的栅极端子的第一电压与经由LED元件耦合到第二晶体管的源极端子的参考电压共同作用，以使第二晶体管不导通，于是LED元件不接收电力。 在足以减少或消除第二晶体管中的渐进阈值偏移的第一预定时间段之后，将第一电压施加到第二晶体管的栅极端子终止。在起伏的背板中稳定tfts

公开(公告)号：WO2006073818A2

公开(公告)日：2006-07-13

申请号：PCT/US2005/046225

申请日：2005-12-20

Applicant: ADVANTECH GLOBAL, LTD. ,  BRODY, Thomas, P. ,  MARCANIO, Joseph, A.

Inventor： BRODY, Thomas, P. ,  MARCANIO, Joseph, A.

IPC: H01L21/4763 ,  C23C16/00

CPC classification number: C23C14/562 ,  C23C14/042 ,  C23C14/5826 ,  C23C14/5873 ,  H01L21/76802 ,  H01L21/76877 ,  Y10T29/41

Abstract: In a shadow mask vapor deposition system, a first conductor is vapor deposited on a substrate and an insulator is vapor deposited on the first conductor. A second conductor is then vapor deposited on at least the insulator. The insulator layer is plasma etched either before or after the vapor deposition of the second conductor to define in the insulator layer a via hole through which at least a portion of the first conductor is exposed. An electrical connection is established between the first and second conductors by way of the via hole.

Abstract translation: 在荫罩气相沉积系统中，将第一导体气相沉积在衬底上，并且在第一导体上蒸镀绝缘体。 然后在至少绝缘体上气相沉积第二导体。 在第二导体的气相沉积之前或之后等离子体蚀刻绝缘体层，以在绝缘体层中限定通孔，第一导体的至少一部分通过该通孔露出。 通过通孔在第一和第二导体之间建立电连接。

公开(公告)号：WO2006023901A2

公开(公告)日：2006-03-02

申请号：PCT/US2005/029920

申请日：2005-08-24

Applicant: ADVANTECH GLOBAL, LTD. ,  BRODY, Thomas, P. ,  MALMBERG, Paul, R. ,  MARCANIO, Joseph, A.

Inventor： BRODY, Thomas, P. ,  MALMBERG, Paul, R. ,  MARCANIO, Joseph, A.

IPC: G09G5/00

CPC classification number: H01L27/3293 ,  G06F3/1446 ,  G09G3/3208 ,  G09G2310/0221 ,  H01L27/3297

Abstract: A scalable tiled display assembly that includes an array of independently addressed actie-matrix organic light-emitting diode (OLED) display tiles cabled to a central control module. Each display tile includes a frame, a driver sub-module, and a flat ribbon cable for connecting the driver sub-module to the display tile. Furthermore, column and row drivers are integrated within each display tile for improved performance and minimal external connections. The invention further includes a method of forming a scalable tiled display system that includes the steps of assembling a plurality of display tile assemblies, determining the viewable area of the display, assembling an array of display tile assemblies according to the desired viewable area, and activating the scalable tiled display system.

Abstract translation: 可扩展的平铺显示组件，其包括连接到中央控制模块的独立寻址的行动矩阵有机发光二极管（OLED）显示瓦阵列。 每个显示瓦片包括框架，驱动器子模块和用于将驱动器子模块连接到显示瓦片的扁平带状电缆。 此外，列和行驱动程序集成在每个显示瓦片内，以提高性能和最小的外部连接。 本发明还包括一种形成可分级的平铺显示系统的方法，该方法包括以下步骤：组装多个显示瓦片组件，确定显示器的可视区域，根据期望的可视区域组装显示瓦片组件阵列，以及激活 可扩展的平铺显示系统。

公开(公告)号：WO2007038427A3

公开(公告)日：2007-04-05

申请号：PCT/US2006/037244

申请日：2006-09-26

Applicant: ADVANTECH GLOBAL, LTD. ,  MARCANIO, Joseph, A. ,  BRODY, Thomas, P.

Inventor： BRODY, Thomas, P.

IPC: H01L21/425

Abstract: Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.

公开(公告)号：WO2006036992A3

公开(公告)日：2007-03-01

申请号：PCT/US2005034700

申请日：2005-09-26

Applicant: ADVANTECH GLOBAL LTD ,  BRODY THOMAS P ,  MALMBERG PAUL R ,  MARCANIO JOSEPH A

Inventor： BRODY THOMAS P ,  MALMBERG PAUL R ,  MARCANIO JOSEPH A

IPC: H01L21/00 ,  H01L31/058

CPC classification number: C23C14/562 ,  C23C14/042 ,  C23C14/541 ,  H01L51/0008 ,  H01L51/0023 ,  H01L51/529 ,  H01L51/56 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for active array temperature sensing and cooling. The system includes an active temperature sensing layer, a thermoelectric cooling layer and a heatsink layer. The temperature sensing layer is formed of temperature sensing elements that sense the temperature gradient across an unevenly heated region of the active array substrate. The thermoelectric cooling layer controls the temperature gradient sensed by the temperature sensing layer. The heatsink layer includes a plurality of cooling channels for absorbing thermal energy from the unevenly heated region. The system is under the control of a process control computer.

Abstract translation: 一种用于有源阵列温度感测和冷却的系统和方法。 该系统包括有源温度感测层，热电冷却层和散热层。 温度感测层由感测有源阵列基板的不均匀加热区域温度梯度的温度感测元件形成。 热电冷却层控制由感温层感测的温度梯度。 散热层包括用于从不均匀加热的区域吸收热能的多个冷却通道。 该系统由过程控制计算机控制。

公开(公告)号：WO2006076237A2

公开(公告)日：2006-07-20

申请号：PCT/US2006/000544

申请日：2006-01-09

Applicant: ADVANTECH GLOBAL, LTD. ,  MARCANIO, Joseph, A. ,  BRODY, Thomas, P.

Inventor： BRODY, Thomas, P.

IPC: G02F1/1343

CPC classification number: G02F1/1362 ,  G02F2001/136231 ,  H01L27/1288

Abstract: An LCD pixel includes a first conductive segment connected to a first bus, a first insulator segment on the first conductive segment, a second conductive segment on the first insulator segment, a liquid crystal material on the second conductive segment, a third conductive segment on the liquid crystal material, and a thin film transistor having a control terminal, a first power terminal and second power terminal connected to a second bus, a third bus and the second conductive segment, respectively. In response to application of a suitable signal on the second bus when reference voltages are present on the first bus and on the third conductive segment, and a voltage is applied to the third bus, the thin film transistor is operative for charging a capacitor formed by the first conductive segment, the first insulator segment and the second conductive segment and for activating the liquid crystal material.

Abstract translation: LCD像素包括连接到第一总线的第一导电部分，第一导电部分上的第一绝缘体部分，第一绝缘体部分上的第二导电部分，第二导电部分上的液晶材料，第二导电部分上的第三导电部分 液晶材料和具有控制端子的薄膜晶体管，分别连接到第二总线，第三总线和第二导电段的第一电源端子和第二电力端子。 响应于在第一总线和第三导电段上存在参考电压时在第二总线上施加合适的信号，并且向第三总线施加电压，薄膜晶体管用于对由 第一导电段，第一绝缘体段和第二导电段，并用于激活液晶材料。

公开(公告)号：WO2006071671A2

公开(公告)日：2006-07-06

申请号：PCT/US2005046348

申请日：2005-12-20

Applicant: ADVANTECH GLOBAL LTD ,  BRODY THOMAS P ,  MARCANIO JOSEPH A ,  CONRAD JEFFREY W ,  COWEN TIMOTHY A

Inventor： BRODY THOMAS P ,  MARCANIO JOSEPH A ,  CONRAD JEFFREY W ,  COWEN TIMOTHY A

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L21/67173 ,  H01L21/67207 ,  H05K1/0393 ,  H05K3/143 ,  H05K3/4076 ,  H05K3/467 ,  H05K2203/1545 ,  Y10S438/944 ,  Y10S438/945

Abstract: Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its edge. The second insulator layer is then deposited on another portion of the first conductor layer in a manner whereupon the second insulator layer slightly overlaps each notch of the first insulator layer, thereby forming the one or more via holes. A conductive filler can optionally be deposited in each via hole. Lastly, a second conductive layer can be deposited over the first insulator layer, the second insulator layer and, if provided, the conductive filler.

Abstract translation: 通过沉积第一导体层并随后在第一导体层的一部分上沉积第一绝缘体层，在连续的在线荫罩制备系统中形成通孔。 以沿其边缘限定至少一个凹口的方式沉积第一绝缘体层。 然后以第二绝缘体层与第一绝缘体层的每个凹口稍微重叠的方式将第二绝缘体层沉积在第一导体层的另一部分上，从而形成一个或多个通孔。 可以任选地在每个通孔中沉积导电填料。 最后，第二导电层可以沉积在第一绝缘体层，第二绝缘体层上，如果提供，则沉积在导电填料上。

公开(公告)号：WO2007133252A3

公开(公告)日：2007-11-22

申请号：PCT/US2006/042858

申请日：2006-11-01

Applicant: ADVANTECH GLOBAL, LTD. ,  MARCANIO, Joseph, A. ,  CONRAD, Jeffrey, W.

Inventor： MARCANIO, Joseph, A. ,  CONRAD, Jeffrey, W.

IPC: B05D1/32 ,  B05D5/00

Abstract: In a method of preparing and using an aperture mask, a temperature of an aperture mask is increased to a first, mounting temperature (T1), whereupon the size of the aperture mask increases according to its coefficient of thermal expansion (CTEam), until at least one dimension thereof is of a first desired extent. The temperature of a frame is also increased to T1, whereupon the size of the frame grows according to its coefficient of thermal expansion (CTEf), which is lower than CTEam. The aperture mask is fixedly mounted to the frame at T1. The frame mounted aperture mask is then used for depositing a material on a substrate at a deposition temperature T2 that is less than T1, whereupon the frame holds the shadow mask in tension with the one dimension at a second desired extent.

公开(公告)号：WO2006073818A3

公开(公告)日：2007-06-21

申请号：PCT/US2005046225

申请日：2005-12-20

Applicant: ADVANTECH GLOBAL LTD ,  BRODY THOMAS P ,  MARCANIO JOSEPH A

Inventor： BRODY THOMAS P ,  MARCANIO JOSEPH A

IPC: H01L23/52

CPC classification number: C23C14/562 ,  C23C14/042 ,  C23C14/5826 ,  C23C14/5873 ,  H01L21/76802 ,  H01L21/76877 ,  Y10T29/41

Abstract: In a shadow mask vapor deposition system, a first conductor (610, Fig. 8A) is vapor deposited on a substrate (114) and an insulator (612) is vapor deposited on the first conductor. A second conductor (614a/614b) is then vapor deposited on at least the insulator (612). The insulator layer (612) is plasma etched either before or after the vapor deposition of the second conductor to define in the insulator layer a via hole (616) through which at least a portion of the first conductor is exposed. An electrical connection is established between the first and second conductors (610 and 614a/614b) by way of the via hole (616).

Abstract translation: 在阴影掩模气相沉积系统中，将第一导体（图8A）蒸镀在衬底（114）上，并且绝缘体（612）被气相沉积在第一导体上。 然后，在至少绝缘体（612）上气相沉积第二导体（614a / 614b）。 在第二导体的气相沉积之前或之后等离子体蚀刻绝缘体层（612），以在绝缘体层中限定通孔（616），第一导体的至少一部分暴露在该通孔中。 通过通孔（616）在第一和第二导体（610和614a / 614b）之间建立电连接。

公开(公告)号：WO2006081352A3

公开(公告)日：2007-04-19

申请号：PCT/US2006002775

申请日：2006-01-26

Applicant: ADVANTECH GLOBAL LTD ,  BRODY THOMAS P ,  MARCANIO JOSEPH A

Inventor： BRODY THOMAS P ,  MARCANIO JOSEPH A

IPC: H01L21/4763

CPC classification number: H01L21/768 ,  H01L21/6715 ,  H01L21/67173 ,  H01L21/67207 ,  H01L21/76802 ,  H05K1/0393 ,  H05K3/143 ,  H05K3/4076 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2203/1545

Abstract: A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) therein, and a vapor deposited conductive filler (320) in the via hole (316) of the first insulator layer (314). Desirably, the conductive filler (320) is deposited in the via hole (316) of the first insulator layer (314) such that the surface of the conductive filler (320) opposite the first conductor layer (312) is substantially planar with the surface of the first insulator layer (314) opposite the first conductor layer (312).

Abstract translation: 多层电子器件可以形成为在绝缘基板（212）上包括绝缘基板（212），第一蒸镀导体层（312），第一导体层上的第一蒸镀绝缘体层（314） 312），其中具有至少一个通孔（316）的第一绝缘体层（314）和在第一绝缘体层（314）的通孔（316）中的气相沉积导电填料（320）。 期望地，导电填料（320）沉积在第一绝缘体层（314）的通孔（316）中，使得与第一导体层（312）相对的导电填料（320）的表面与表面 与第一导体层（312）相对的第一绝缘体层（314）。