公开(公告)号：WO2014098966A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/044440

申请日：2013-06-06

Applicant: INTEL CORPORATION

Inventor： ROY, Mihir, K. ,  LOTZ, Stephanie, M. ,  JEN, Wei-Lun, Kane

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract translation: 描述允许使用有机桥的多芯片互连的实施例。 在一些实施例中，有机封装衬底具有嵌入式有机桥。 有机桥可以具有允许通过有机桥连接管芯的互连结构。 在一些实施例中，有机桥包括金属布线层，金属衬垫层和交错的有机聚合物电介质层，但没有衬底层。 只有几层的实施例可以嵌入到有机封装衬底的顶层或顶层几层中。 还描述了制造方法。

公开(公告)号：WO2013031822A1

公开(公告)日：2013-03-07

申请号：PCT/JP2012/071816

申请日：2012-08-29

Applicant: 京セラ株式会社 ,  橋本 利弘

Inventor： 橋本　利弘

IPC: H05K3/46 ,  G01R1/073 ,  G01R31/26

CPC classification number: H05K1/0306 ,  G01R1/07314 ,  G01R31/2886 ,  H05K1/0271 ,  H05K3/4605 ,  H05K3/467 ,  H05K3/4673 ,  H05K2203/061

Abstract: 　上面を有するセラミック基板１およびセラミック基板の上面に設けられた配線導体11を含むベースＢと、セラミック基板１の上面に順次積層された接合層２および薄膜配線層３と、接合層２を厚み方向に貫通しているとともに配線導体11と薄膜配線層３とを電気的に接続している貫通導体23とを有しており、接合層２は、熱硬化性樹脂からなるコア層21と、コア層21を形成する熱硬化性樹脂よりも弾性率が小さい熱硬化性樹脂からなる、コア層21の上下面に積層された接着層22とを含んでいる薄膜配線基板である。コア層21によって接合層２の変形を抑制することができ、貫通導体23と薄膜導体層31および配線導体11との電気的な接続を良好に確保できる。また、接着層22により接合層２の接着性を確保できる。

Abstract translation: 薄膜配线基板具有包括具有顶面的陶瓷基板（1）和设置在陶瓷基板的顶面的配线导体（11）的基体（B），接合层（2）和薄层 连续地层叠在陶瓷基板（1）的上表面的通孔布线层（3）和将布线导体（11）和薄膜布线层（3）电穿孔的通孔导体（23） 接合层（2）在厚度方向上。 接合层（2）是由由热硬化树脂构成的芯层（21）和粘合层（22）构成的薄膜布线基板，所述粘合层由具有较小的弹性系数的热硬化树脂构成 所述加热硬化树脂形成所述芯层（21），并且层压在所述芯层（21）的上表面和下表面上。 芯层（21）可以抑制粘合层（2）的变形。 可以确保贯通导体（23）和薄膜导体层（31）与布线导体（11）的良好电连接。 此外，可以通过粘合剂层（22）确保接合层（2）的粘合性。

公开(公告)号：WO2009056235A3

公开(公告)日：2009-08-27

申请号：PCT/EP2008008778

申请日：2008-10-16

Applicant: INTERPANE ENTW & BERATUNGSGES ,  GFE FREMAT GMBH ,  BEREK HARRY ,  PAUL ALEXANDER ,  SCHMIDT STEFFEN ,  HERLITZE LOTHAR ,  WEIS HANSJOERG ,  HAEUSER KARL

Inventor： BEREK HARRY ,  PAUL ALEXANDER ,  SCHMIDT STEFFEN ,  HERLITZE LOTHAR ,  WEIS HANSJOERG ,  HAEUSER KARL

IPC: H01C1/14 ,  C23C24/04 ,  H01G4/228 ,  H01G9/20 ,  H01L21/768 ,  H05K3/14

CPC classification number: H01C1/14 ,  C23C24/04 ,  C23C28/321 ,  C23C28/322 ,  C23C28/3225 ,  C23C28/34 ,  C23C28/345 ,  C23C28/3455 ,  H01G4/228 ,  H01L31/022425 ,  H01L31/0296 ,  H01L31/0322 ,  H01L31/03685 ,  H01L31/03762 ,  H01L31/0392 ,  H01L31/03923 ,  H01L31/03925 ,  H05K1/0306 ,  H05K3/4007 ,  H05K3/467 ,  H05K2201/0367 ,  H05K2203/1344 ,  Y02E10/541 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

Abstract: The invention relates to a layer system comprising a contact element (5) and a substrate (1). A multilayer system (14) that is disposed on the substrate (1) has at least one top layer (3; 4) and a bottom layer (2; 3) as well as a contact element (5) which penetrates the at least one top layer (3; 4) and contacts the bottom layer (2; 3). The invention further relates to a method for producing a contact element (5) of a multilayer system (14).

Abstract translation: 本发明涉及具有包括衬底（1）的接触元件（5）的层系统。 A中的基板（1）上设置的多层系统（14）具有至少一个上（3; 4）;在层和接触元件（5），其包括至少一个上部层（3; 4）和底部（3 2）渗透 和下层（2; 3）接触。 本发明还涉及用于制造用于多层系统（14）的接触元件（5）的方法。

公开(公告)号：WO2006071671A2

公开(公告)日：2006-07-06

申请号：PCT/US2005046348

申请日：2005-12-20

Applicant: ADVANTECH GLOBAL LTD ,  BRODY THOMAS P ,  MARCANIO JOSEPH A ,  CONRAD JEFFREY W ,  COWEN TIMOTHY A

Inventor： BRODY THOMAS P ,  MARCANIO JOSEPH A ,  CONRAD JEFFREY W ,  COWEN TIMOTHY A

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L21/67173 ,  H01L21/67207 ,  H05K1/0393 ,  H05K3/143 ,  H05K3/4076 ,  H05K3/467 ,  H05K2203/1545 ,  Y10S438/944 ,  Y10S438/945

Abstract: Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its edge. The second insulator layer is then deposited on another portion of the first conductor layer in a manner whereupon the second insulator layer slightly overlaps each notch of the first insulator layer, thereby forming the one or more via holes. A conductive filler can optionally be deposited in each via hole. Lastly, a second conductive layer can be deposited over the first insulator layer, the second insulator layer and, if provided, the conductive filler.

Abstract translation: 通过沉积第一导体层并随后在第一导体层的一部分上沉积第一绝缘体层，在连续的在线荫罩制备系统中形成通孔。 以沿其边缘限定至少一个凹口的方式沉积第一绝缘体层。 然后以第二绝缘体层与第一绝缘体层的每个凹口稍微重叠的方式将第二绝缘体层沉积在第一导体层的另一部分上，从而形成一个或多个通孔。 可以任选地在每个通孔中沉积导电填料。 最后，第二导电层可以沉积在第一绝缘体层，第二绝缘体层上，如果提供，则沉积在导电填料上。

公开(公告)号：WO2005114720A3

公开(公告)日：2006-06-15

申请号：PCT/US2005017224

申请日：2005-05-16

Applicant: CALIFORNIA INST OF TECHN ,  UNIV SOUTHERN CALIFORNIA ,  RODGER DAMIEN C ,  HUMAYUN MARK ,  TAI YU-CHONG ,  WEILAND JAMES D

Inventor： RODGER DAMIEN C ,  HUMAYUN MARK ,  TAI YU-CHONG ,  WEILAND JAMES D

IPC: H01L21/50 ,  A61N1/05 ,  H01L29/40 ,  H05K1/00 ,  H05K1/03 ,  H05K3/00 ,  H05K3/04 ,  H05K3/46

CPC classification number: H05K1/032 ,  A61N1/04 ,  A61N1/0543 ,  A61N1/0551 ,  H05K1/0393 ,  H05K3/0041 ,  H05K3/007 ,  H05K3/048 ,  H05K3/467 ,  H05K3/4682 ,  H05K2201/0179 ,  H05K2203/016

Abstract: Method for manufacturing a parylene-based electrode array that includes an underlying parylene layer, one or more patterned electrode layers comprising a conductive material such as a metal, and one or more overlying parylene layers. The overlying parylene is etched away or otherwise processed to expose the electrodes where stimulation or recording is to occur. All other conductive material in the device is occluded from the environment by the two layers of parylene surrounding it.

Abstract translation: 制造聚对二甲苯基电极阵列的方法，其包括下面的聚对二甲苯层，一个或多个图案化的电极层，包括导电材料如金属和一个或多个上覆的聚对二甲苯层。 将上覆的聚对二甲苯蚀刻掉或以其他方式处理，以暴露要进行刺激或记录的电极。 器件中的所有其他导电材料都被围绕它的两层聚对二甲苯从环境中吸收。

公开(公告)号：WO2005053367A3

公开(公告)日：2005-08-25

申请号：PCT/GB2004004205

申请日：2004-10-01

Applicant: YAZAKI EUROPE LTD ,  OGILVIE WILLIAM

Inventor： OGILVIE WILLIAM

IPC: H05K1/00 ,  H05K3/10 ,  H05K3/14 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/388 ,  H05K1/0284 ,  H05K3/102 ,  H05K3/14 ,  H05K3/467

Abstract: A method of manufacturing a patterned electric circuit. The method comprises the steps of providing a cold gas-dynamic spraying (CGDS) device, providing a substrate, and depositing a pattern of electrically conductive material with the CGDS device on the substrate by relative movement between the CGDS device to the substrate.

Abstract translation: 一种图案化电路的制造方法。 该方法包括以下步骤：通过CGDS器件与衬底之间的相对运动，提供冷气体动态喷涂（CGDS）器件，提供衬底，以及通过CGDS器件在衬底上沉积导电材料图案。

公开(公告)号：WO1996022008A1

公开(公告)日：1996-07-18

申请号：PCT/JP1996000021

申请日：1996-01-10

Applicant: HITACHI, LTD. ,  AKIBA, Yutaka ,  NARIZUKA, Yasunori ,  TANEI, Hirayoshi ,  KITAMURA, Naoya

Inventor： HITACHI, LTD.

IPC: H05K03/46

CPC classification number: H05K1/0246 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/092 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/167 ,  H05K3/403 ,  H05K3/4053 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/467 ,  H05K9/0039 ,  H05K2201/0209 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed. This invention can remarkably suppress unwanted radiation by absorbing the potential fluctuation (resonance) which occurs in a power supply loop by equivalently reducing the Q-value of the stray capacitance, absorbing the standing wave by the parallel plate lines matchedly terminated and, closing and shielding the parallel plate lines.

Abstract translation: 通过将电源层的电位波动相对于在切换IC器件等而发生的接地层的电位波动转换为基底中的焦耳热而不使用任何部件作为对策来实现高安装密度的低EMI电路 针对EMI。 还公开了其结构，使用它的电路板以及制造电路板的方法。 从电源层和接地层观察的固体层之间的杂散电容的Q值的平行板线等效地减少，并且通过形成其中电阻器（电阻层）和另一接地层的结构匹配地终止 除了在多层电路板上的电源层和接地层之外提供。 还公开了封闭的屏蔽结构。 本发明通过吸收电源回路中发生的电位波动（谐振）可以显着地抑制不期望的辐射，通过等效地降低杂散电容的Q值，吸收平行板线匹配终止的驻波，闭合屏蔽 平行板线。

公开(公告)号：WO1993012539A1

公开(公告)日：1993-06-24

申请号：PCT/US1992011122

申请日：1992-12-18

Applicant: RAYCHEM CORPORATION

Inventor： RAYCHEM CORPORATION ,  CHAZAN, David, Joel ,  WEIHE, Gary, Roy ,  OTTE, Richard, F.

IPC: H01L23/367

CPC classification number: H01L23/367 ,  H01L21/486 ,  H01L23/3677 ,  H01L2224/32225 ,  H05K1/0206 ,  H05K1/0306 ,  H05K3/0035 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/10674 ,  H05K2203/0733

Abstract: Thermal post vias are formed within a formed multilayer, high density interconnect including a base and plural layers of metal conductors (68, 72, 76) separated by dielectric material (70) by the steps of: removing in a single step dielectric material at predetermined sites of the thermal post vias to define substantially cylindrical post holes, and forming the thermal post vias by emplacing conductor material, such as metal, into the post holes so that the material fully occupies and fills up the holes.

公开(公告)号：WO1992009102A1

公开(公告)日：1992-05-29

申请号：PCT/US1991000703

申请日：1991-02-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHANG, Kenneth ,  CZORNYJ, George ,  FAROOQ, Mukta, Shaji ,  KUMAR, Ananda, Hosakere ,  PITTLER, Marvin, S. +di ,  STEIMEL, Heinz, Otto

IPC: H01L21/48

CPC classification number: H01L21/76808 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/76807 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/184 ,  H05K3/388 ,  H05K3/465 ,  H05K3/4661 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/107

Abstract: A method of making a multilayer thin film structure on the surface of a dielectric substrate which includes the steps of: a) forming a multilayer thin film structure including the steps of: applying a first layer of dielectric polymeric material on the surface of a dielectric substrate, applying a second layer of dielectric polymeric material over the first layer of polymeric material wherein the second polymeric material is photosensitive, imagewise exposing and developing the second polymeric material to form a feature therein, the second layer feature in communication with at least one feature formed in the first polymeric material; and b) filling the features in the entire multilayer structure simultaneously with conductive material. Preferably, the first layer feature is a via and the second layer feature is a capture pad or wiring channel. Also disclosed is a multilayer thin film structure made by this method.

Abstract translation: 一种在电介质基板的表面上制造多层薄膜结构的方法，包括以下步骤：a）形成多层薄膜结构，其包括以下步骤：将第一层电介质聚合物材料施加到介电基片的表面上 在所述第一聚合物材料层上施加第二层电介质聚合材料，其中所述第二聚合物材料是光敏的，成像曝光和显影所述第二聚合物材料以在其中形成特征，所述第二层特征与形成的至少一个特征相连通 在第一种聚合材料中; 以及b）与导电材料同时填充整个多层结构中的特征。 优选地，第一层特征是通孔，第二层特征是捕获垫或布线通道。 还公开了通过该方法制造的多层薄膜结构。

公开(公告)号：WO2015200008A1

公开(公告)日：2015-12-30

申请号：PCT/US2015/035541

申请日：2015-06-12

Applicant: 3M INNOVATIVE PROPERTIES COMPANY

Inventor： SEBASTIAN, Muthu ,  TAN, Fong Liang

IPC: B32B7/02 ,  G06F3/041 ,  H01B1/02 ,  H01B5/14

CPC classification number: H05K3/467 ,  C23C14/00 ,  C23C14/083 ,  C23C14/14 ,  C23C14/34 ,  C23C18/165 ,  C23C18/1689 ,  C23C18/38 ,  C23C18/42 ,  C25D3/38 ,  C25D3/46 ,  C25D5/48 ,  C25D5/54 ,  C25D7/00 ,  G03F7/2002 ,  G03F7/40 ,  G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  H01L31/1884 ,  H05K1/0274 ,  H05K1/09 ,  H05K3/064 ,  H05K3/067 ,  H05K3/16 ,  H05K3/381 ,  H05K3/388 ,  H05K2201/0108 ,  H05K2201/0326 ,  H05K2201/10128

Abstract: The present disclosure provides a method to provide a conductive bus bar on a patterned transparent conductor, such as ITO traces used for touch screen manufacturing. The method can be a cheaper and a more convenient technique to pattern a conductive metal or metal alloy, such as copper, silver, or a copper/silver/titanium alloy, on ITO electrodes in a roll-to-roll process.

Abstract translation: 本公开提供了一种在图案化的透明导体（例如用于触摸屏制造的ITO迹线）上提供导电母线的方法。 该方法可以是在卷对卷方法中在ITO电极上图案化导电金属或金属合金（例如铜，银或铜/银/钛合金）的更便宜和更方便的技术。