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    PHASED-ARRAY TRANSCEIVER
    1.
    发明申请
    PHASED-ARRAY TRANSCEIVER 审中-公开
    同步阵列收发器

    公开(公告)号：WO2013038276A1

    公开(公告)日：2013-03-21

    申请号：PCT/IB2012/053142

    申请日：2012-06-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED ,  REYNOLDS, Scott, Kevin ,  LIU, Duixian ,  NATARAJAN, Arun, Sridhar ,  VALDES GARCIA, Alberto ,  FRIEDMAN, Daniel, Joseph

    Inventor： REYNOLDS, Scott, Kevin ,  LIU, Duixian ,  NATARAJAN, Arun, Sridhar ,  VALDES GARCIA, Alberto ,  FRIEDMAN, Daniel, Joseph

    IPC: H01Q1/00 ,  H01L23/538

    CPC classification number: H01Q21/061 ,  H01L2224/16225 ,  H01Q21/065 ,  H01Q23/00 ,  H04B7/04 ,  Y10T29/49016

    Abstract: Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.

    Abstract translation: 公开了针对收发器设备的系统，方法，设备和设备。 根据一种方法，选择电路封装的电路布局的一组部分的第一部分中的第一组天线位置。 该方法还包括在电路布局的另一部分中选择另一组天线位置，使得另一组的所选择的天线位置的布置与先前选择的一组天线位置的选定天线位置的布置不同。 迭代在另一部分中选择另一组位置，直到对天线总数进行选择。 执行另一组的选择，使得另一部分中的连续未选定位置不超过预定数量的位置。 此外，天线元件形成在所选择的位置以制造电路封装。

    A DIFFERENTIAL CROSS-COUPLED POWER COMBINER OR DIVIDER
    3.
    发明申请
    A DIFFERENTIAL CROSS-COUPLED POWER COMBINER OR DIVIDER 审中-公开
    一个差分的交叉耦合动力组合机或分岔机

    公开(公告)号：WO2011029720A1

    公开(公告)日：2011-03-17

    申请号：PCT/EP2010/062349

    申请日：2010-08-24

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  FLOYD, Brian ,  NATARAJAN, Arun, Sridhar ,  REYNOLDS, Scott, Kevin ,  SOYUER, Mehmet ,  VALDES GARCIA, Alberto

    Inventor： FLOYD, Brian ,  NATARAJAN, Arun, Sridhar ,  REYNOLDS, Scott, Kevin ,  SOYUER, Mehmet ,  VALDES GARCIA, Alberto

    IPC: H01P5/16

    CPC classification number: H01P5/16

    Abstract: A differential cross-coupled power combiner in one aspect comprises a plurality of inputs, an output, a plurality of differential transmission lines each coupled between a corresponding one of the inputs and the output, and at least one set of additional differential transmission lines arranged in series between any two of the inputs. First and second ones of the additional differential transmission lines in the set are coupled to one another using a cross- coupling arrangement. Other aspects of the invention provide a differential cross-coupled power divider, communication system receivers and transmitters incorporating respective power combiners and dividers, and integrated circuit implementations of power combiners and dividers.

    Abstract translation: 差分交叉耦合功率组合器在一个方面包括多个输入，输出，多个差分传输线，每个差分传输线分别耦合在相应的一个输入端和输出端之间，以及至少一组附加差分传输线路，其布置在 任何两个输入之间的串联。 组中的第一和第二附加差动传输线使用交叉耦合布置彼此耦合。 本发明的其它方面提供了差分交叉耦合功率分配器，包含各个功率组合器和分频器的通信系统接收器和发射器以及功率组合器和分频器的集成电路实现。

    A mm-WAVE FULLY INTEGRATED PHASED ARRAY RECEIVER AND TRANSMITTER WITH ON CHIP ANTENNAS
    4.
    发明申请
    A mm-WAVE FULLY INTEGRATED PHASED ARRAY RECEIVER AND TRANSMITTER WITH ON CHIP ANTENNAS 审中-公开
    一个毫米波的完全集成的相位阵列接收器和发射器与芯片天线

    公开(公告)号：WO2007038310A1

    公开(公告)日：2007-04-05

    申请号：PCT/US2006/037050

    申请日：2006-09-22

    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY ,  BABAKHANI, Aydin ,  GUAN, Xiang ,  HAJIMIRI, Seyed, Ali ,  KOMIJANI, Abbas ,  NATARAJAN, Arun

    Inventor： BABAKHANI, Aydin ,  GUAN, Xiang ,  HAJIMIRI, Seyed, Ali ,  KOMIJANI, Abbas ,  NATARAJAN, Arun

    IPC: G01S7/03

    CPC classification number: H01Q9/065 ,  G01S7/032 ,  H01Q19/065

    Abstract: A phased array mm-wave device includes a substrate, a mm-wave transmitter integrated onto the substrate configured to transmit a mm-wave signal and/or a mm-wave receiver integrated onto the substrate and configured to receive a mm-wave signal. The mm-wave device also includes a phased array antenna system integrated onto the substrate and including two or more antenna elements. The phased array mm-wave device also includes one or more dielectric lenses. A distributed mm-wave distributed combining tree circuit includes at least two pairs of differential tranconductors with regenerative degeneration and accepts at least two differential input signals. Two mm-wave loopback methods measure the phased array antenna patterns and the performance of an integrated receiver transmitter system.

    Abstract translation: 相控阵mm波装置包括基板，集成在基板上的毫米波发射器，该波长发射器被配置成传输一毫米波信号和/或集成在基板上的毫米波接收器，并被配置为接收毫米波信号。 毫米波器件还包括集成在衬底上并包括两个或多个天线元件的相控阵天线系统。 相控阵mm波装置还包括一个或多个电介质透镜。 分布式的毫米波分布式组合树电路包括具有再生退化的至少两对差分导体并且接受至少两个差分输入信号。 两毫米波回环方法测量相控阵天线方向图和综合接收发射机系统的性能。

    PHASE SHIFTER AND RELATED LOAD DEVICE WITH LINEARIZATION TECHNIQUE EMPLOYED THEREIN
    5.
    发明申请
    PHASE SHIFTER AND RELATED LOAD DEVICE WITH LINEARIZATION TECHNIQUE EMPLOYED THEREIN 审中-公开
    具有线性化技术的相位变换器及相关负载装置

    公开(公告)号：WO2011017829A1

    公开(公告)日：2011-02-17

    申请号：PCT/CN2009/073156

    申请日：2009-08-10

    Applicant: MEDIATEK INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  TSAI, Ming-da ,  ZHAN, Jing-hong, Conan ,  NATARAJAN, Arun

    Inventor： TSAI, Ming-da ,  ZHAN, Jing-hong, Conan ,  NATARAJAN, Arun

    IPC: H03H7/18

    CPC classification number: H03H7/20

    Abstract: A phase shifter includes a phase shifter core and load devices. The phase shifter core has an input port for receiving an input signal, an output port for outputting an output signal, and connection ports. The load devices are coupled to the connection ports, respectively. At leas t one of the load devices includes first varactor units each having a first node and a second node, where first nodes of the first varactor units are coupled to a first voltage, second nodes of the first varactor units are respectively coupled to a plurality of second voltages, and the second voltages include at least two voltages different from each other.

    Abstract translation: 移相器包括移相器核和负载装置。 移相器核具有用于接收输入信号的输入端口，用于输出输出信号的输出端口和连接端口。 负载装置分别耦合到连接端口。 在其中一个负载装置包括第一变容二极管单元，每个具有第一节点和第二节点，其中第一变容二极管单元的第一节点耦合到第一电压，第一变容二极管单元的第二节点分别耦合到多个 的第二电压，并且第二电压包括彼此不同的至少两个电压。

    MULTI-ELEMENT PHASED ARRAY TRANSMITTER WITH LO PHASE SHIFTING AND INTEGRATED POWER AMPLIFIER
    6.
    发明申请
    MULTI-ELEMENT PHASED ARRAY TRANSMITTER WITH LO PHASE SHIFTING AND INTEGRATED POWER AMPLIFIER 审中-公开
    多元相位阵发射机，具有相移和集成功率放大器

    公开(公告)号：WO2006039500A3

    公开(公告)日：2007-01-18

    申请号：PCT/US2005035210

    申请日：2005-09-29

    Applicant: CALIFORNIA INST OF TECHN ,  NATARAJAN ARUN ,  KOMIJANI ABBAS ,  HAJIMIRI SEYED ALI

    Inventor： NATARAJAN ARUN ,  KOMIJANI ABBAS ,  HAJIMIRI SEYED ALI

    IPC: H04B1/02 ,  H04B7/02 ,  H04M1/00

    CPC classification number: H01Q3/42 ,  H01Q3/22

    Abstract: A fully integrated CMOS multi-element phased-array transmitter (transmitter)includes, in part, on-chip power amplifiers (PA) (262), with integrated output matching. The transmitter is adapted to be configured as a two-dimensional 2-by-2 array or as a one dimensional l-by-4 array. The transmitter uses a two step up-conversion architecture with an IF frequency of 4.8GHz. Double-quadrature architecture for the up-conversion stages attenuates the signal at image frequencies. The phase selectors (252, 254) in each transmitter path have independent access to all the phases of the VCO (202). The double quadrature architecture results in two sets of phase selectors for each path, one for the in-phase (1) and one for the quadrature phase (Q) of the LO signal. The phase selection is done in two stages, with the first stage determining the desired VCO differential phase pair and the next stage selecting the appropriate polarity. An on-chip Balun is used for differential to single-ended conversion.

    Abstract translation: 完全集成的CMOS多元件相控阵发射器（发射机）部分地包括片上功率放大器（PA）（262），具有集成的输出匹配。 发射机适于配置为二维2×2阵列或一维1/4乘法阵列。 发射机采用两段升频转换架构，中频频率为4.8GHz。 上转换级的双正交架构在图像频率衰减信号。 每个发射机路径中的相位选择器（252,254）具有对VCO（202）的所有相位的独立访问。 双正交架构为每个路径产生两组相位选择器，一组用于同相（1），另一组用于LO信号的正交相位（Q）。 相位选择分为两个阶段，第一阶段确定期望的VCO差分相位对，下一个阶段选择适当的极性。 片内平衡管用于差分到单端转换。

    MULTI-ELEMENT PHASED ARRAY TRANSMITTER WITH LO PHASE SHIFTING AND INTEGRATED POWER AMPLIFIER
    7.
    发明申请
    MULTI-ELEMENT PHASED ARRAY TRANSMITTER WITH LO PHASE SHIFTING AND INTEGRATED POWER AMPLIFIER 审中-公开
    多元相位阵发射机，具有相移和集成功率放大器

    公开(公告)号：WO2006039500A2

    公开(公告)日：2006-04-13

    申请号：PCT/US2005/035210

    申请日：2005-09-29

    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY ,  NATARAJAN, Arun ,  KOMIJANI, Abbas ,  HAJIMIRI, Seyed, Ali

    Inventor： NATARAJAN, Arun ,  KOMIJANI, Abbas ,  HAJIMIRI, Seyed, Ali

    IPC: H01Q3/22

    CPC classification number: H01Q3/42 ,  H01Q3/22

    Abstract: A fully integrated CMOS multi-element phased-array transmitter (transmitter) includes, in part, on-chip power amplifiers (PA), with integrated output matching. The transmitter is adapted to be configured as a two-dimensional 2-by-2 array or as a one dimensional 1-by-4 array. The transmitter uses a two step up-conversion architecture with an IF frequency of 4.8GHz. Double-quadrature architecture for the up-conversion stages attenuates the signal at image frequencies. The phase selectors in each transmitter path have independent access to all the phases of the VCO. The double quadrature architecture results in two sets of phase selectors for each path, one for the in-phase (I) and one for the quadrature phase (Q) of the LO signal. The phase selection is done in two stages, with the first stage determining the desired VCO differential phase pair and the next stage selecting the appropriate polarity. An on-chip Balun is used for differential to single-ended conversion.

    Abstract translation: 完全集成的CMOS多元件相控阵发射器（发射机）部分包括片上功率放大器（PA），具有集成的输出匹配。 发射机适于配置为二维2×2阵列或一维1×4阵列。 发射机采用双频上变频架构，中频频率为4.8GHz。 上转换级的双正交架构衰减了图像频率处的信号。 每个发射器路径中的相位选择器具有对VCO的所有相位的独立访问。 双正交架构为每个路径产生两组相位选择器，一组用于同相（I），另一组用于LO信号的正交相位（Q）。 相位选择分为两个阶段，第一阶段确定期望的VCO差分相位对，下一个阶段选择适当的极性。 片内平衡变换器用于差分到单端转换。

    PHASE SHIFTING AND COMBINING ARCHITECTURE FOR PHASED ARRAYS
    10.
    发明申请
    PHASE SHIFTING AND COMBINING ARCHITECTURE FOR PHASED ARRAYS 审中-公开
    相移阵列和相位阵列的组合结构

    公开(公告)号：WO2008083212A1

    公开(公告)日：2008-07-10

    申请号：PCT/US2007/088928

    申请日：2007-12-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIO N ,  FLOYD, Brian, Allan ,  NATARAJAN, Arun, Sridhar

    Inventor： FLOYD, Brian, Allan ,  NATARAJAN, Arun, Sridhar

    IPC: G01S13/00

    CPC classification number: H01Q21/0037 ,  H01Q3/30

    Abstract: Improved phased array techniques and architectures are provided. For example, a linear phased array includes N discrete phase shifters and N-I variable phase shifters, wherein the N-I variable phase shifters are respectively coupled between adjacent output nodes of the N discrete phase shifters such that the N discrete phase shifters reduce an amount of continuous phase shift provided by the N-I variable phase shifters. Each of the N discrete phase shifters may select between two or more discrete phase shifts. The N discrete phase shifters also preferably eliminate a need for a variable termination impedance in the linear phased array.

    Abstract translation: 提供了改进的相控阵技术和架构。 例如，线性相控阵列包括N个离散移相器和NI可变移相器，其中NI可变移相器分别耦合在N个离散移相器的相邻输出节点之间，使得N个离散移相器减少连续相位 由NI可变移相器提供的移位。 N个离散移相器中的每一个可以在两个或更多个离散相移之间进行选择。 N个离散移相器还优选地消除对线性相控阵列中的可变终端阻抗的需要。

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