公开(公告)号：WO2013028827A1

公开(公告)日：2013-02-28

申请号：PCT/US2012/052000

申请日：2012-08-23

Applicant: RAMBUS INC. ,  PEREGO, Richard, E. ,  LINSTADT, John, Eric ,  BATRA, Pradeep ,  BROOKS, John, Welsford ,  WOO, Steven ,  LAI, Lawrence

Inventor： PEREGO, Richard, E. ,  LINSTADT, John, Eric ,  BATRA, Pradeep ,  BROOKS, John, Welsford ,  WOO, Steven ,  LAI, Lawrence

IPC: G06F13/14 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract translation: 存储器系统包括将命令和地址传送到主存储器模块的CPU。 该模块包括缓冲电路，用于中继CPU和主存储器之间的命令和数据。 存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持外围功能，例如图形处理，以改善整体系统性能。 缓冲电路有助于CPU和外围处理器之间的指令和数据通信，以最小化或消除修改CPU的需要，从而减少采用具有集成处理能力的主存储器模块的实际障碍。

公开(公告)号：WO2013028854A1

公开(公告)日：2013-02-28

申请号：PCT/US2012/052052

申请日：2012-08-23

Applicant: Rambus Inc. ,  PEREGO, Richard, E. ,  BATRA, Pradeep ,  WOO, Steven ,  LAI, Lawrence ,  YEUNG, Chi-Ming

Inventor： PEREGO, Richard, E. ,  BATRA, Pradeep ,  WOO, Steven ,  LAI, Lawrence ,  YEUNG, Chi-Ming

IPC: G06F13/14 ,  G06F13/38 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract translation: 存储器系统包括将命令和地址传送到主存储器模块的CPU。 该模块包含一个缓冲电路，用于在CPU和主存储器之间中继命令和数据。 存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持诸如图形处理等外围功能，以提高整体系统性能。 缓冲电路有助于CPU和外设处理器之间的指令和数据通信，其方式可以最大限度地减少或消除修改CPU的需求，从而降低采用具有集成处理能力的主内存模块的实际障碍。

公开(公告)号：WO2010117535A2

公开(公告)日：2010-10-14

申请号：PCT/US2010/026757

申请日：2010-03-10

Applicant: RAMBUS INC. ,  WARE, Frederick A. ,  BROOKS, John Welsford ,  KASAMSETTY, Kishore Ven ,  PEREGO, Richard E.

Inventor： WARE, Frederick A. ,  BROOKS, John Welsford ,  KASAMSETTY, Kishore Ven ,  PEREGO, Richard E.

IPC: G06F13/16 ,  G06F12/02 ,  G06F9/30

CPC classification number: G06F13/161

Abstract: The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device.

Abstract translation: 本实施例提供了一种被配置为从存储器控制器向存储器件发送请求的存储器系统，其中该请求包括独立的激活和预充电命令。 activate命令与行地址相关联，该行地址标识了activate命令的第一行。 响应于激活命令，系统激活存储器设备中的第一组中的第一行。 类似地，响应于预充电命令，系统对存储器件中的第二存储体进行预充电。

公开(公告)号：WO2009067386A1

公开(公告)日：2009-05-28

申请号：PCT/US2008/083626

申请日：2008-11-14

Applicant: RAMBUS INC. ,  CHANG, Kun-Yung ,  SHEN, Jie ,  LEE, Hae-Chang ,  ASSADERAGHI, Fariborz ,  PEREGO, Richard, E. ,  CHUN, Jung-Hoon

Inventor： CHANG, Kun-Yung ,  SHEN, Jie ,  LEE, Hae-Chang ,  ASSADERAGHI, Fariborz ,  PEREGO, Richard, E. ,  CHUN, Jung-Hoon

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation.

Abstract translation: 描述了具有发送和接收操作模式的位分片电路。 所述位片电路包括：第一发射电路和在第一时钟域中操作的第一接收电路，其中所述第一电路接收第一时钟信号; 第二发送电路和在第二时钟域中操作的第二接收电路，其中所述第二电路接收第二时钟信号; 发射转换电路和接收转换电路，所述发射转换电路将所述第一发射电路耦合到所述第二发射电路，所述接收转换电路将所述第一接收电路耦合到所述第二接收电路，其中所述转换电路接收所述第一和第二时钟信号; 以及产生所述第二时钟信号的单相混频器，其中所述第二时钟信号具有所述发送操作模式中的第一相位和所述接收操作模式中的第二相位。

公开(公告)号：WO2008153652A3

公开(公告)日：2009-02-05

申请号：PCT/US2008005985

申请日：2008-05-08

Applicant: RAMBUS INC ,  KIZER JADE M ,  PEREGO RICHARD E

Inventor： KIZER JADE M ,  PEREGO RICHARD E

IPC: G11C7/10 ,  G11C7/22 ,  H04L7/033

CPC classification number: G11C7/22 ,  G11C7/222 ,  H03L7/0891 ,  H03L7/18

Abstract: A memory system (100) includes a memory controller (105) that issues command signals and a reference-clock signal to a memory device (110). The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.

Abstract translation: 存储器系统（100）包括向存储器件（110）发出命令信号和参考时钟信号的存储器控​​制器（105）。 参考时钟信号的边沿速率低于命令信号的比特率，因此存储器件将参考时钟信号相乘以产生用于对输入的命令信号进行采样的命令恢复时钟信号。 存储器控制器将命令信号发出为与参考时钟信号的边缘对准的一系列多位命令字，使得存储器件可以使用参考时钟信号的边沿进行命令字对准。

公开(公告)号：WO2005072329A2

公开(公告)日：2005-08-11

申请号：PCT/US2005002301

申请日：2005-01-25

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  PEREGO RICHARD E ,  HAMPEL CRAIG E

Inventor： WARE FREDERICK A ,  PEREGO RICHARD E ,  HAMPEL CRAIG E

IPC: H04B1/38 ,  H04L1/24 ,  H04L7/10 ,  H04L27/00

CPC classification number: H04L1/242 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12 ,  H04L27/00

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract translation: 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

公开(公告)号：WO2005072299A2

公开(公告)日：2005-08-11

申请号：PCT/US2005/002139

申请日：2005-01-25

Applicant: RAMBUS, INC. ,  HAMPEL, Craig, E. ,  WARE, Frederick, A. ,  PEREGO, Richard, E.

Inventor： HAMPEL, Craig, E. ,  WARE, Frederick, A. ,  PEREGO, Richard, E.

IPC: H04B1/38 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2 N -1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Abstract translation: 一种提供执行第一校准序列的方法和系统，例如在系统初始化时建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量 在参数中漂移，并根据测量的漂移更新操作值。 与第一校准序列相比，第二校准序列使用较少的通信信道资源。 在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2 N比特的伪随机比特序列，其中N等于 大于等于7，而第二校准序列使用短校准模式，例如小于16字节的固定码，例如短至2字节长。

公开(公告)号：WO2010117535A3

公开(公告)日：2011-02-03

申请号：PCT/US2010026757

申请日：2010-03-10

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  BROOKS JOHN WELSFORD ,  KASAMSETTY KISHORE VEN ,  PEREGO RICHARD E

Inventor： WARE FREDERICK A ,  BROOKS JOHN WELSFORD ,  KASAMSETTY KISHORE VEN ,  PEREGO RICHARD E

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02

CPC classification number: G06F13/161

Abstract: The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device.

Abstract translation: 本实施例提供一种存储器系统，其被配置为从存储器控制器向存储器件发送请求，其中该请求包括独立的激活和预充电命令。 activate命令与一个行地址相关联，该地址标识了activate命令的第一行。 响应于激活命令，系统激活存储器设备中第一组中的第一行。 类似地，响应于预充电命令，系统对存储器件中的第二存储体进行预充电。

公开(公告)号：WO2009067496A4

公开(公告)日：2009-07-16

申请号：PCT/US2008084003

申请日：2008-11-19

Applicant: RAMBUS INC ,  PEREGO RICHARD E

Inventor： PEREGO RICHARD E

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: Transmission of a signal is scheduled to avoid sending the signal during a designated event associated with another signal. For example, the time at which a signal is transmitted may be scheduled to avoid a turnaround time period of a bidirectional signal path. This technique may be employed, for example, in a memory system where a memory controller communicates with one or more memory devices or memory modules. Here, the memory system may be configured to avoid sending memory request signals during a driver turnaround window corresponding to when a bidirectional memory data interface switches from being driven by the memory controller to being driven by a memory device/module, or vice versa.

Abstract translation: 计划发送信号以避免在与另一信号相关联的指定事件期间发送信号。 例如，可以调度发送信号的时间以避免双向信号路径的周转时间周期。 例如，可以在存储器控制器与一个或多个存储器设备或存储器模块通信的存储器系统中采用该技术。 这里，存储器系统可以被配置为避免在驱动器转向窗口期间发送存储器请求信号，该窗口对应于双向存储器数据接口从存储器控制器驱动切换到由存储器设备/模块驱动时，或反之亦然。

公开(公告)号：WO2008127698A3

公开(公告)日：2009-03-26

申请号：PCT/US2008004790

申请日：2008-04-11

Applicant: RAMBUS INC ,  PEREGO RICHARD E ,  WARE FREDERICK A

Inventor： PEREGO RICHARD E ,  WARE FREDERICK A

IPC: G11C5/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract translation: 存储器系统包括具有多个存储器 - 控制器块的存储器控​​制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。 请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。 所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。 每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。