公开(公告)号：WO2007037929A3

公开(公告)日：2007-10-25

申请号：PCT/US2006034771

申请日：2006-09-06

Applicant: FREESCALE SEMICONDUCTOR INC ,  ADETUTU OLUBUNMI O ,  LUO TIEN YING ,  RAMANI NARAYANAN C

Inventor： ADETUTU OLUBUNMI O ,  LUO TIEN YING ,  RAMANI NARAYANAN C

IPC: H01L29/76

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: A transistor structure of an electronic device (10) can include a gate dielectric layer (22) and a gate electrode (82). The gate electrode (82) can have a surface portion (32) between the gate dielectric layer (22) and the rest of the gate electrode (42, 62, 72). The surface portion (32) can be formed such that another portion (42) of the gate electrode primarily sets the effective work function in the finished transistor structure (82).

Abstract translation: 电子器件（10）的晶体管结构可以包括栅极介电层（22）和栅电极（82）。 栅极电极（82）可以在栅介质层（22）和栅极电极（42,62,72）的其余部分之间具有表面部分（32）。 表面部分（32）可以形成为使得栅电极的另一部分（42）主要在最终晶体管结构（82）中设置有效功函数。

公开(公告)号：WO2007092657A2

公开(公告)日：2007-08-16

申请号：PCT/US2007060367

申请日：2007-01-11

Applicant: FREESCALE SEMICONDUCTOR INC ,  LUO TIEN YING ,  ADETUTU OLUBUNMI O ,  LUCKOWSKI ERIC D ,  RAMANI NARAYANAN C

Inventor： LUO TIEN YING ,  ADETUTU OLUBUNMI O ,  LUCKOWSKI ERIC D ,  RAMANI NARAYANAN C

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a semiconductor device, the method includes forming a gate dielectric (104) over the semiconductor substrate, exposing the gate dielectric to a halogen, and incorporating the halogen into the gate dielectric (106). In one embodiment, the halogen is fluorine. In one embodiment, the gate dielectric is also exposed to nitrogen and the nitrogen is incorporated into the gate dielectric (108). In one embodiment, the gate dielectric is a metal oxide.

Abstract translation: 一种形成半导体器件的方法，所述方法包括在所述半导体衬底上形成栅极电介质（104），将所述栅极电介质暴露于卤素，并将所述卤素结合到所述栅极电介质（106）中。 在一个实施方案中，卤素是氟。 在一个实施例中，栅极电介质也暴露于氮气，并且氮被并入到栅极电介质（108）中。 在一个实施例中，栅极电介质是金属氧化物。

公开(公告)号：WO2008002710A1

公开(公告)日：2008-01-03

申请号：PCT/US2007/066122

申请日：2007-04-06

Applicant: FREESCALE SEMICONDUCTOR INC. ,  SPENCER, Gregory S. ,  FILIPIAK, Stanley M. ,  RAMANI, Narayanan C. ,  TURNER, Michael D.

Inventor： SPENCER, Gregory S. ,  FILIPIAK, Stanley M. ,  RAMANI, Narayanan C. ,  TURNER, Michael D.

IPC: H01L21/26 ,  H01L21/335 ,  H01L21/336

CPC classification number: H01L21/268 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A strained semiconductor layer (12) is achieved by an overlying stressed dielectric layer (34). The stress in the dielectric layer (34) is increased by a radiation anneal (36). The radiation anneal (36) can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously. The heat is intense, preferably 900-1400 degrees Celcius, but for a very short duration of less than 10 milliseconds; preferably about 1 millisecond or even shorter. The result of the radiation anneal (36) can also be used to activate the source/drain. Thus, this type of radiation anneal can result in a larger change in stress, activation of the source/drain, and still no expansion of the source/drain (26, 28).

Abstract translation: 应变半导体层（12）通过覆盖的应力介电层（34）实现。 电介质层（34）中的应力通过辐射退火（36）增加。 辐射退火（36）可以是通过使用激光束进行扫描或者同时向整个电介质层提供退火的闪光工具。 热量很强，最好是900-1400摄氏度，但持续时间不到10毫秒; 优选约1毫秒甚至更短。 辐射退火（36）的结果也可用于激活源极/漏极。 因此，这种类型的辐射退火可以导致应力的变化更大，源极/漏极的激活，并且仍然没有源极/漏极（26,28）的膨胀。

公开(公告)号：WO2008014032A1

公开(公告)日：2008-01-31

申请号：PCT/US2007/068098

申请日：2007-05-03

Applicant: FREESCALE SEMICONDUCTOR INC. ,  SPENCER, Gregory, S. ,  KOLAGUNTA, Venkat, R. ,  RAMANI, Narayanan, C. ,  TRIVEDI, Vishal, P.

Inventor： SPENCER, Gregory, S. ,  KOLAGUNTA, Venkat, R. ,  RAMANI, Narayanan, C. ,  TRIVEDI, Vishal, P.

IPC: H01L31/117

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6653 ,  H01L29/7843

Abstract: A strained semiconductor layer (18) is achieved by a method for transferring stress from a dielectric layer (30) to a semiconductor layer (18). The method comprises providing a substrate (12) having a semiconductor layer (18). A dielectric layer (30) having a stress is formed over the semiconductor layer (18). A radiation anneal (32) is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer (30) to create a stress in the semiconductor layer (18). The dielectric layer (30) may then be removed. At least a portion of the stress in the semiconductor layer (18) remains in the semiconductor layer after the dielectric layer (30) is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions (26, 28).

Abstract translation: 应变半导体层（18）通过用于将应力从介电层（30）传递到半导体层（18）的方法来实现。 该方法包括提供具有半导体层（18）的衬底（12）。 在半导体层（18）上形成具有应力的电介质层（30）。 辐射退火（32）施加在电介质层上，持续时间不超过10毫秒，导致电介质层（30）的应力在半导体层（18）中产生应力。 然后可以去除电介质层（30）。 在去除电介质层（30）之后，半导体层（18）中的应力的至少一部分保留在半导体层中。 辐射退火可以通过使用激光束或闪光工具。 辐射退火也可用于激活源/漏区（26,28）。

公开(公告)号：WO2007092657A3

公开(公告)日：2007-08-16

申请号：PCT/US2007/060367

申请日：2007-01-11

Applicant: FREESCALE SEMICONDUCTOR INC. ,  LUO, Tien, Ying ,  ADETUTU, Olubunmi, O. ,  LUCKOWSKI, Eric, D. ,  RAMANI, Narayanan, C.

Inventor： LUO, Tien, Ying ,  ADETUTU, Olubunmi, O. ,  LUCKOWSKI, Eric, D. ,  RAMANI, Narayanan, C.

IPC: H01L21/8234

Abstract: A method of forming a semiconductor device, the method includes forming a gate dielectric (104) over the semiconductor substrate, exposing the gate dielectric to a halogen, and incorporating the halogen into the gate dielectric (106). In one embodiment, the halogen is fluorine. In one embodiment, the gate dielectric is also exposed to nitrogen and the nitrogen is incorporated into the gate dielectric (108). In one embodiment, the gate dielectric is a metal oxide.

公开(公告)号：WO2007037929A2

公开(公告)日：2007-04-05

申请号：PCT/US2006/034771

申请日：2006-09-06

Applicant: FREESCALE SEMICONDUCTOR ,  ADETUTU, Olubunmi O. ,  LUO, Tien Ying ,  RAMANI, Narayanan C.

Inventor： ADETUTU, Olubunmi O. ,  LUO, Tien Ying ,  RAMANI, Narayanan C.

IPC: H01L29/76

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: A transistor structure of an electronic device (10) can include a gate dielectric layer (22) and a gate electrode (82). The gate electrode (82) can have a surface portion (32) between the gate dielectric layer (22) and the rest of the gate electrode (42, 62, 72). The surface portion (32) can be formed such that another portion (42) of the gate electrode primarily sets the effective work function in the finished transistor structure (82).

Abstract translation: 电子器件（10）的晶体管结构可以包括栅极电介质层（22）和栅极电极（82）。 栅电极（82）可以在栅介质层（22）和栅电极（42,62,72）的其余部分之间具有表面部分（32）。 表面部分（32）可以形成为使得栅电极的另一部分（42）主要在完成的晶体管结构（82）中设定有效功函数。