公开(公告)号：WO2009134412A1

公开(公告)日：2009-11-05

申请号：PCT/US2009/002669

申请日：2009-04-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  WIECZOREK, Karsten ,  RUTTLOFF, Kerstin

Inventor： HORSTMANN, Manfred ,  JAVORKA, Peter ,  WIECZOREK, Karsten ,  RUTTLOFF, Kerstin

IPC: H01L21/8238 ,  H01L21/02

CPC classification number: H01L21/823828 ,  H01L21/02068 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823835 ,  H01L21/823871

Abstract: A method is disclosed which includes implanting an inert species in a layer of a gate electrode material (205A), the gate electrode material being formed above a substrate (201) and having a P-doped layer portion and an N-doped layer portion, forming a first gate electrode (205P) from the P-doped layer portion and a second gate electrode (205N) from the N-doped layer portion, performing a wet chemical cleaning process, and forming a first transistor (200B) on the basis of the first gate electrode (205P) and a second transistor (200A) on the basis of the second gate electrode (205N).

Abstract translation: 公开了一种方法，其包括在栅电极材料（205A）的层中注入惰性物质，栅电极材料形成在衬底（201）上方并具有P掺杂层部分和N掺杂层部分， 从所述P掺杂层部分形成第一栅电极（205P），从所述N掺杂层部分形成第二栅电极（205N），进行湿化学清洗处理，以及基于 基于第二栅电极（205N）的第一栅电极（205P）和第二晶体管（200A）。

公开(公告)号：WO2009108370A1

公开(公告)日：2009-09-03

申请号：PCT/US2009/001287

申请日：2009-02-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  HUEBLER, Peter ,  RUTTLOFF, Kerstin

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  HUEBLER, Peter ,  RUTTLOFF, Kerstin

IPC: H01L21/768 ,  H01L21/8238

CPC classification number: H01L21/76826 ,  H01L21/76832 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843 ,  Y02P80/30

Abstract: In a dual stress liner approach, an intermediate etch stop material (234) may be provided on the basis of a plasma-assisted oxidation process (250) rather than by deposition so the corresponding thickness (234T) of the etch stop material (234) may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices (200).

Abstract translation: 在双重应力衬里方法中，可以基于等离子体辅助氧化工艺（250）而不是通过沉积来提供中间蚀刻停止材料（234），使得蚀刻停止材料（234）的对应厚度（234T） 可能会减少。 因此，与常规策略相比，所产生的纵横比可能不那么明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件（200）。

公开(公告)号：WO2010037521A1

公开(公告)日：2010-04-08

申请号：PCT/EP2009/007000

申请日：2009-09-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  BEYER, Sven ,  FROHBERG, Kai ,  REICHE, Katrin ,  RUTTLOFF, Kerstin

Inventor： BEYER, Sven ,  FROHBERG, Kai ,  REICHE, Katrin ,  RUTTLOFF, Kerstin

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A contact element may be formed on the basis of a hard mask (233), which may be patterned on the basis of a first resist mask (210) and on the basis of a second resist mask (211), so as to define an appropriate intersection area (234) which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.

Abstract translation: 可以基于硬掩模（233）形成接触元件，该硬掩模可以基于第一抗蚀剂掩模（210）并基于第二抗蚀剂掩模（211）被图案化，以便限定一个 可以表示接触元件的最终设计尺寸的适当交叉区域（234）。 因此，可以基于具有较少限制性约束的光刻工艺来形成每个抗蚀剂掩模，因为在两个抗蚀剂掩模中的每一个中可选择至少一个横向尺寸作为非临界尺寸。