公开(公告)号：WO2007064472A1

公开(公告)日：2007-06-07

申请号：PCT/US2006/044292

申请日：2006-11-15

Applicant: ADVANCED MICRO DEVICES, INC. ,  HOENTSCHEL, Jan ,  WEI, Andy ,  HEINZE, Mario ,  JAVORKA, Peter

Inventor： HOENTSCHEL, Jan ,  WEI, Andy ,  HEINZE, Mario ,  JAVORKA, Peter

IPC: H01L21/336 ,  H01L21/265

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

Abstract: By performing a tilted amorphization implantation (208, 308P, 308N) and a subsequent re-crystallization on the basis of a stressed overlying material (209, 211, 309, 311, 319S), a highly efficient strain-inducing mechanism is provided. The tilted amorphization implantation (208, 308P, 308N) may result in a significantly reduced defect rate during the re-crystallization process, thereby substantially reducing leakage currents in sophisticated transistor elements (200, 300N, 300P).

Abstract translation: 通过基于应力覆盖材料（209,211,309,311,319S）进行倾斜非晶化注入（208,308P，308N）和随后的重结晶，提供了一种高效应变诱发机制。 倾斜的非晶化注入（208,308P，308N）可能导致在再结晶过程期间显着降低的缺陷率，从而大大降低复杂晶体管元件（200,300N，300P）中的漏电流。

公开(公告)号：WO2009134412A1

公开(公告)日：2009-11-05

申请号：PCT/US2009/002669

申请日：2009-04-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  WIECZOREK, Karsten ,  RUTTLOFF, Kerstin

Inventor： HORSTMANN, Manfred ,  JAVORKA, Peter ,  WIECZOREK, Karsten ,  RUTTLOFF, Kerstin

IPC: H01L21/8238 ,  H01L21/02

CPC classification number: H01L21/823828 ,  H01L21/02068 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823835 ,  H01L21/823871

Abstract: A method is disclosed which includes implanting an inert species in a layer of a gate electrode material (205A), the gate electrode material being formed above a substrate (201) and having a P-doped layer portion and an N-doped layer portion, forming a first gate electrode (205P) from the P-doped layer portion and a second gate electrode (205N) from the N-doped layer portion, performing a wet chemical cleaning process, and forming a first transistor (200B) on the basis of the first gate electrode (205P) and a second transistor (200A) on the basis of the second gate electrode (205N).

Abstract translation: 公开了一种方法，其包括在栅电极材料（205A）的层中注入惰性物质，栅电极材料形成在衬底（201）上方并具有P掺杂层部分和N掺杂层部分， 从所述P掺杂层部分形成第一栅电极（205P），从所述N掺杂层部分形成第二栅电极（205N），进行湿化学清洗处理，以及基于 基于第二栅电极（205N）的第一栅电极（205P）和第二晶体管（200A）。

公开(公告)号：WO2008042144A3

公开(公告)日：2008-08-14

申请号：PCT/US2007020598

申请日：2007-09-24

Applicant: ADVANCED MICRO DEVICES INC ,  SCHWAN CHRISTOPH ,  BLOOMQUIST JOE ,  JAVORKA PETER ,  HORSTMANN MANFRED ,  BEYER SVEN ,  FORSBERG MARKUS ,  WIRBELEIT FRANK ,  ROMERO KARLA

Inventor： SCHWAN CHRISTOPH ,  BLOOMQUIST JOE ,  JAVORKA PETER ,  HORSTMANN MANFRED ,  BEYER SVEN ,  FORSBERG MARKUS ,  WIRBELEIT FRANK ,  ROMERO KARLA

IPC: H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

Abstract: By forming isolation trenches (102 A, 102B) of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions (105A, 105B) may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material (107A, 107B) including compressive and tensile stress may be appropriately provided in the respective isolation trenches (102A, 102B) in order to correspondingly adapt the charge carrier mobility of respective channel regions (121 A, 121B).

Abstract translation: 通过基于不同的工艺顺序形成不同类型的固有应力的隔离沟槽（102A，102B），可以调整相邻的有源半导体区域（105A，105B）的应变特性以获得整体器件性能。 例如，可以在各个隔离沟槽（102A，102B）中适当地提供包括压缩应力和拉伸应力的高应力介电填充材料（107A，107B），以便相应地适配各个沟道区域（121A，121B）的电荷载流子迁移率 ）。

公开(公告)号：WO2011013080A1

公开(公告)日：2011-02-03

申请号：PCT/IB2010/053437

申请日：2010-07-28

Applicant: GLOBALFOUNDRIES INC. ,  KAMMLER, Thorsten ,  WIATR, Maciej ,  BOSCHKE, Roman ,  JAVORKA, Peter

Inventor： KAMMLER, Thorsten ,  WIATR, Maciej ,  BOSCHKE, Roman ,  JAVORKA, Peter

IPC: H01L21/8238 ,  H01L21/8239 ,  H01L21/8244 ,  H01L27/02 ,  H01L27/105 ,  H01L27/11 ,  H01L21/768

CPC classification number: H01L21/823871 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104

Abstract: In a static memory cell, the failure rate upon forming contact elements connecting an active region (202C) with a gate electrode structure (210A) formed above an isolation region (203) may be significantly reduced by incorporating an implantation species at a tip portion of the active region (202C) through a sidewalS (203S) of the isolation trench (203T) prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region (202C),

Abstract translation: 在静态存储单元中，在形成在隔离区（203）上方的有源区（202C）与栅电极结构（210A）连接的接触元件的故障率可以通过在 通过隔离沟槽（203T）的侧壁（203S），在用绝缘材料填充之前，有源区域（202C）。 注入物质可以表示P型掺杂物种类和/或用于显着改变活性区域（202C）的尖端部分的材料特性的惰性物质，

公开(公告)号：WO2008042144A2

公开(公告)日：2008-04-10

申请号：PCT/US2007/020598

申请日：2007-09-24

Applicant: ADVANCED MICRO DEVICES, INC. ,  SCHWAN, Christoph ,  BLOOMQUIST, Joe ,  JAVORKA, Peter ,  HORSTMANN, Manfred ,  BEYER, Sven ,  FORSBERG, Markus ,  WIRBELEIT, Frank ,  ROMERO, Karla

Inventor： SCHWAN, Christoph ,  BLOOMQUIST, Joe ,  JAVORKA, Peter ,  HORSTMANN, Manfred ,  BEYER, Sven ,  FORSBERG, Markus ,  WIRBELEIT, Frank ,  ROMERO, Karla

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

Abstract: By forming isolation trenches (102 A, 102B) of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions (105A, 105B) may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material (107A, 107B) including compressive and tensile stress may be appropriately provided in the respective isolation trenches (102A, 102B) in order to correspondingly adapt the charge carrier mobility of respective channel regions (121 A, 121B).

Abstract translation: 通过基于分离的工艺顺序形成不同类型的固有应力的隔离沟槽（102A，102B），可以调节相邻的有源半导体区域（105A，105B）的应变特性以获得整体器件性能。 例如，可以在相应的隔离沟槽（102A，102B）中适当地提供包括压应力和拉伸应力的高应力电介质填充材料（107A，107B），以便相应地适应相应通道区域（121A，121B）的载流子迁移率 ）。

公开(公告)号：WO2007126495A1

公开(公告)日：2007-11-08

申请号：PCT/US2007/004689

申请日：2007-02-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  BLOOMQUIST, Joe

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  BLOOMQUIST, Joe

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/665 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: By recessing (112D, 212D) drain and source regions (114, 214), a highly stressed layer (118, 218), such as a contact etch stop layer, may be formed in the recess (112, 212) in order to enhance the strain generation in the adjacent channel region (104, 204) of a field effect transistor (100, 200). Moreover, a strained semiconductor material (230) may be positioned in close proximity to the channel region (104, 204) by reducing or avoiding undue relaxation effects of metal suicides (217), thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain- inducing mechanism.

Abstract translation: 通过凹陷（112D，212D）漏极和源极区域（114,214），可以在凹部（112,212）中形成高应力层（118,218），例如接触蚀刻停止层，以便增强 在场效应晶体管（100,200）的相邻沟道区（104,204）中产生应变。 此外，应变半导体材料（230）可以通过减少或避免金属硅化物（217）的不适当的松弛效应来定位在通道区域（104,204）附近，从而也为应变产生提供更高的效率。 在一些方面，两种效应可以组合以获得更有效的应变诱导机制。