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    SUBTRACTIVE PLUG ETCHING
    1.
    发明申请
    SUBTRACTIVE PLUG ETCHING 审中-公开

    公开(公告)号：WO2018125109A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2016/069083

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： LIN, Kevin ,  BRISTOL, Robert L. ,  CHANDHOK, Manish

    IPC: H01L21/768

    CPC classification number: H01L21/76885 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897

    Abstract: In an example, there is disclosed a method of manufacturing an integrated circuit, including: depositing a metal interconnect layer on an interlayer dielectric (ILD) including an ILD material, including a first interconnect and a second interconnect; depositing a first cross grating having a first dielectric material; depositing a second cross grating having a second dielectric material, the second cross grating substantially perpendicular to the first cross grating; subtractively etching a plug pattern between the first interconnect and the second interconnect; filling the plug pattern with a plug dielectric material; and depositing a via to electrically couple the second interconnect to a different layer.

    METAL OXIDE NANOPARTICLES AS FILLABLE HARDMASK MATERIALS
    3.
    发明申请
    METAL OXIDE NANOPARTICLES AS FILLABLE HARDMASK MATERIALS 审中-公开
    金属氧化物纳米粒子作为可填充的硬质材料

    公开(公告)号：WO2018063402A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/055025

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： KRYSAK, Marie ,  GSTREIN, Florian ,  CHANDHOK, Manish

    IPC: H01L21/033 ,  G03F7/20 ,  H01L21/768

    CPC classification number: H01L21/0332 ,  C01F7/00 ,  C01F7/02 ,  C01G19/02 ,  C01G23/04 ,  C01G25/02 ,  C01G27/02 ,  C01P2004/64 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76897

    Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.

    Abstract translation: 包含金属氧化物颗粒的介电组合物，所述金属氧化物颗粒包含以至少1：1的比率用有机配体封端的5纳米或更小的直径。 一种包括合成直径为5纳米或更小的金属氧化物颗粒的方法; 并用有机配体以至少1：1的比例将金属氧化物颗粒封盖。 一种方法，包括：在半导体衬底上形成互连层; 在所述互连层上形成第一硬掩模材料和不同的第二硬掩模材料，其中所述第一硬掩模材料和所述第二硬掩模材料中的至少一个形成在用于通孔台的目标互连层的区域之上，并且所述第一 硬掩模材料和第二硬掩模材料包括金属氧化物纳米粒子; 以及选择性地通过第一硬掩模材料和第二硬掩模材料之一形成到互连层的开口。

    FORMING SELF-ALIGNED VERTICAL INTERCONNECT ACCESSES (VIAS) IN INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS (ICS)
    4.
    发明申请
    FORMING SELF-ALIGNED VERTICAL INTERCONNECT ACCESSES (VIAS) IN INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS (ICS) 审中-公开
    在集成电路互连结构（ICS）中形成自对准垂直互连接入（VIAS）

    公开(公告)号：WO2017165206A1

    公开(公告)日：2017-09-28

    申请号：PCT/US2017/022868

    申请日：2017-03-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： XU, Jeffrey, Junhao ,  ZHU, John, Jianhong ,  YEAP, Choh, Fei

    IPC: H01L21/768

    CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/49827 ,  H01L23/49894

    Abstract: Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.

    Abstract translation: 公开了在集成电路（IC）的互连结构中形成自对准垂直互连访问（通孔）。 为了减少或避免通孔未对准下面的互连金属线，在互连结构中制造通孔以与下面的互连金属线自对准。 就此而言，下层金属线形成在电介质层中。 凹槽形成在层间电介质的顶表面下方的下层金属线中。 停止层设置在层间电介质上方和下层金属线的凹槽内。 停止层允许在下面的金属线的凹槽内形成（例如，蚀刻）通孔隧道以使通孔隧道与下面的金属线自对准。 然后将导电材料沉积在延伸到凹陷中的通孔隧道中以形成互连到下面的金属线的自对准通孔。

    TRIBLOCK COPOLYMERS FOR SELF-ALIGNING VIAS OR CONTACTS
    5.
    发明申请
    TRIBLOCK COPOLYMERS FOR SELF-ALIGNING VIAS OR CONTACTS 审中-公开
    用于自对准VIAS或联系的三嵌段共聚物

    公开(公告)号：WO2017111926A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2015/067203

    申请日：2015-12-21

    Applicant: INTEL CORPORATION

    Inventor： YOUNKIN, Todd R. ,  HAN, Eungnak ,  HARLSON, Shane M. ,  BLACKWELL, James M.

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76897 ,  H01L23/48 ,  H01L23/5329 ,  H01L23/53295

    Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive. The method also includes irradiating and developing select locations of the third segregated block component to provide via openings over the metal lines of the lower metallization layer.

    Abstract translation: 描述了用于形成自对准通孔或用于线互连的后端的接触的基于三嵌段共聚物的制造方案以及所得到的结构。 在一个实例中，制造用于半导体管芯的互连结构的方法包括在衬底上方形成包括交替的金属线和电介质线的下金属化层。 该方法还包括在下金属化层上方形成三嵌段共聚物层。 该方法还包括分离三嵌段共聚物层以在下金属化层的电介质线上方形成第一分离块部件，并且形成设置在下金属化层的金属线上方的交替的第二和第三分离块部件，其中第三 分离的嵌段组分是光敏的。 该方法还包括照射和显影第三分离块部件的选择位置，以在下金属化层的金属线上提供通孔开口。

    TECHNIQUES FOR FORMING ELECTRICALLY CONDUCTIVE FEATURES WITH IMPROVED ALIGNMENT AND CAPACITANCE REDUCTION
    6.
    发明申请
    TECHNIQUES FOR FORMING ELECTRICALLY CONDUCTIVE FEATURES WITH IMPROVED ALIGNMENT AND CAPACITANCE REDUCTION 审中-公开
    形成具有改善的对准和电容降低的导电特性的技术

    公开(公告)号：WO2017111847A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2015/000413

    申请日：2015-12-24

    Applicant: INTEL CORPORATION

    Inventor： LIN, Kevin ,  SCHENKER, Richard, E. ,  CHANDHOK, Manish ,  BIELEFELD, Jeffery

    IPC: H01L21/768

    CPC classification number: H01L21/76834 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53295

    Abstract: Techniques are disclosed for forming electrically conductive features with improved alignment and capacitance reduction. In accordance with some embodiments, individual conductive features may be formed over a semiconductor substrate by a damascene process. For a given feature, first and second barrier layers (conformal or otherwise) may be disposed along sidewalls thereof, and a helmet-like hardmask body may be disposed over a top surface thereof. Additional conductive features can be formed between existing features, using the barrier layers as alignment spacers, thereby halving (or otherwise reducing) feature pitch. A layer of another hardmask material may be disposed over the additionally formed features. That layer and the helmet-like hardmask bodies may be of different material composition, providing for etch selectivity with respect to one another. Additional layer(s) can be formed over the resultant topography, exploiting the hardmask etch selectivity in forming interconnects for adjacent integrated circuit layers.

    Abstract translation: 公开了用于形成具有改进的对准和电容减小的导电特征的技术。 根据一些实施例，可以通过镶嵌工艺在半导体衬底上形成各个导电特征。 对于给定的特征，第一和第二阻挡层（保形或其他）可以沿其侧壁布置，并且头盔状硬掩模主体可以布置在其顶表面上方。 可以在现有特征之间形成额外的导电特征，使用阻挡层作为对准间隔件，由此使特征间距减半（或以其他方式减小）。 一层另一种硬掩模材料可以设置在附加形成的特征上。 该层和头盔状硬掩模主体可以具有不同的材料组成，从而相对于彼此提供蚀刻选择性。 附加层可以形成在合成地形上，利用硬掩模蚀刻选择性形成用于相邻集成电路层的互连。

    METHODS, APPARATUSES AND SYSTEMS FOR INTEGRATED CIRCUIT STRUCTURES WITH A REPLACEMENT INTER-LAYER DIELECTRIC (ILD)
    7.
    发明申请
    METHODS, APPARATUSES AND SYSTEMS FOR INTEGRATED CIRCUIT STRUCTURES WITH A REPLACEMENT INTER-LAYER DIELECTRIC (ILD) 审中-公开
    具有替代层间电介质（ILD）的集成电路结构的方法，装置和系统

    公开(公告)号：WO2017052559A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2015/052003

    申请日：2015-09-24

    Applicant: INTEL CORPORATION

    Inventor： SINGH, Kanwaljit ,  LIN, Kevin ,  CHAWLA, Jasmeet, S. ,  SCHENKER, Richard

    IPC: H01L21/31

    CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897

    Abstract: Embodiments of the present disclosure describe techniques and configurations associated with an integrated circuit (IC) structure with a replacement inter-layer dielectric (ILD) layer disposed on a first ILD layer. A sacrificial layer may be formed on the first ILD layer. Trenches may be patterned and formed in the sacrificial layer such that the trenches are disposed on the first ILD layer. Vias may be patterned and formed in the first ILD layer below the trenches. After formation of the trenches, the sacrificial layer may be removed, and the replacement ILD layer (e.g., a second ILD layer) may be formed on the first ILD layer between the trenches. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了与集成电路（IC）结构相关联的技术和配置，其中置换在第一ILD层上的置换层间电介质（ILD）层。 可以在第一ILD层上形成牺牲层。 沟槽可以被图案化并形成在牺牲层中，使得沟槽设置在第一ILD层上。 可以在沟槽下方的第一ILD层中图案化并形成通孔。 在形成沟槽之后，可以去除牺牲层，并且可以在沟槽之间的第一ILD层上形成置换的ILD层（例如，第二ILD层）。 可以描述和/或要求保护其他实施例。

    SELF-ALIGNED PROCESS
    10.
    发明申请
    SELF-ALIGNED PROCESS 审中-公开
    自对准过程

    公开(公告)号：WO2016111811A1

    公开(公告)日：2016-07-14

    申请号：PCT/US2015/065719

    申请日：2015-12-15

    Applicant: APPLIED MATERIALS, INC

    Inventor： PANDIT, Mandar B. ,  WANG, Anchuan ,  INGLE, Nitin K.

    IPC: H01L21/68

    CPC classification number: H01J37/32412 ,  H01J37/32357 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897

    Abstract: Methods of forming self-aligned structures on patterned substrates are described. The methods may be used to form metal lines or vias without the use of a separate photolithography pattern definition operation. Self-aligned contacts may be produced regardless of the presence of spacer elements. The methods include directionally ion-implanting a gapfill portion of a gapfill silicon oxide layer to implant into the gapfill portion without substantially ion-implanting the remainder of the gapfill silicon oxide layer (the sidewalls). Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that the gapfill portions of silicon oxide are selectively etched relative to other exposed portions exposed parallel to the ion implantation direction. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.

    Abstract translation: 描述了在图案化衬底上形成自对准结构的方法。 该方法可用于形成金属线或通孔而不使用单独的光刻图案定义操作。 可以产生自对准的触点，而不管间隔元件的存在。 所述方法包括定向地离子注入间隙填充氧化硅层的间隙填充部分以注入到间隙填充部分中，而基本上不离子注入间隙填充氧化硅层（侧壁）的剩余部分。 随后，使用含氟前体形成远程等离子体以蚀刻图案化衬底，使得相对于平行于离子注入方向暴露的其它暴露部分选择性地蚀刻氧化硅的间隙填充部分。 在没有离子注入的情况下，蚀刻操作将是各向同性的，这是由于在蚀刻过程期间等离子体激发的远端特性。

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