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    FABRICATING NANOWIRE TRANSISTORS USING DIRECTIONAL SELECTIVE ETCHING
    2.
    发明申请
    FABRICATING NANOWIRE TRANSISTORS USING DIRECTIONAL SELECTIVE ETCHING 审中-公开
    用方向选择性蚀刻法制作纳米晶体管

    公开(公告)号：WO2018063314A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/054730

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： MISTKAWI, Nabil G. ,  GLASS, Glenn A.

    IPC: H01L29/78 ,  H01L29/73 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423

    CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0924 ,  H01L29/1079 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/73 ,  H01L29/775 ,  H01L29/78696

    Abstract: Techniques are disclosed for fabricating nanowire transistors using directional selective etching. Generally, a selective wet etch employing a given etchant can be used to remove at least one "select material" while not removing other material exposed to the etch (or removing that other material at a relatively slower rate). The techniques described herein expand upon such selective etch processing by including a directional component. A directional selective etch may include a selective etch that only (or primarily) removes the select material in a targeted direction and/or that discriminates against removal of material in a non-targeted direction. For instance, one or more SiGe nanowires can be formed from a stack of alternating sacrificial Si and non-sacrificial SiGe layers, where a directional selective etch removes the sacrificial Si layer(s) in a horizontal direction without adversely affecting exposed sub-channel/sub-fin Si (by using an etchant that discriminates against removing Si in a vertical direction).

    Abstract translation: 公开了使用定向选择性蚀刻来制造纳米线晶体管的技术。 通常，使用给定蚀刻剂的选择性湿法蚀刻可用于去除至少一种“选择材料” 同时不去除暴露于蚀刻的其他材料（或以相对较慢的速率去除其他材料）。 这里描述的技术通过包括方向分量来扩展这种选择性蚀刻处理。 定向选择性蚀刻可以包括选择性蚀刻，该选择性蚀刻仅在目标方向上（或主要）去除选择材料和/或区分不在非目标方向上去除材料。 例如，一个或多个SiGe纳米线可以由交替的牺牲Si和非牺牲SiGe层的叠层形成，其中定向选择性蚀刻沿水平方向去除牺牲Si层而不会不利地影响暴露的子沟道/ 子鳍Si（通过使用区分在垂直方向上去除Si的蚀刻剂）。

    半导体结构及其制造方法
    7.
    发明申请
    半导体结构及其制造方法 审中-公开

    公开(公告)号：WO2014056277A1

    公开(公告)日：2014-04-17

    申请号：PCT/CN2012/085343

    申请日：2012-11-27

    Applicant: 中国科学院微电子研究所

    Inventor： 朱慧珑 ,  尹海洲 ,  骆志炯

    IPC: H01L21/336 ,  H01L29/06

    CPC classification number: H01L29/7848 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78654

    Abstract: 提供一种半导体结构及其制造方法。半导体结构包括衬底（130）、栅堆叠、侧墙（240）、基底区（100）、源/漏区以及支撑隔离结构（123），其中：基底区（100）位于衬底（130）上方并通过空腔（112）与衬底（130）之间隔离；支撑隔离结构（123）位于空腔（112）的两侧，其中，部分支撑隔离结构（123）与衬底（130）相连接；栅堆叠位于基底区（100）之上，侧墙（240）环绕栅堆叠；源/漏区位于栅堆叠、基底区（100）和支撑隔离结构（123）的两侧，其中，源/漏区中的应力沿高度方向由下至上先逐步增加再逐步降低。本发明利于抑制短沟道效应，以及向沟道提供最优的应力效果。

    HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS
    8.
    发明申请
    HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS 审中-公开
    具有介电衬底的高电压三维器件

    公开(公告)号：WO2014004012A2

    公开(公告)日：2014-01-03

    申请号：PCT/US2013/044363

    申请日：2013-06-05

    Applicant: INTEL CORPORATION (a corporation of Delaware)

    Inventor： HAFEZ, Walid M. ,  YEH, Jeng-Ya D. ,  TSAI, Curtis ,  PARK, Joodong ,  JAN, Chia-Hong ,  BHIMARASETTI, Gopinath

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

    Abstract translation: 描述了具有电介质衬里的高电压三维器件和形成具有电介质衬里的高电压三维器件的方法。 例如，半导体结构包括设置在衬底上的第一鳍状有源区和第二鳍状有源区。 第一栅极结构设置在第一鳍状件有源区的顶表面上方并且沿着第一鳍状件有源区的侧壁。 第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。 第一栅极电介质由布置在第一鳍状有源区上并且沿着第一隔离物的侧壁的第一电介质层以及布置在第一电介质层上并且沿着第一隔离物的侧壁布置的不同的第二电介质层组成。 该半导体结构还包括第二栅极结构，该第二栅极结构设置在第二鳍状有源区的顶表面上方并且沿着第二鳍状有源区的侧壁。 第二栅极结构包括第二栅极电介质，第二栅极电极和第二间隔物。 第二栅极电介质由设置在第二鳍状有源区上并且沿着第二隔离物的侧壁的第二电介质层构成。

    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    9.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
    半导体结构及其形成方法

    公开(公告)号：WO2012163048A1

    公开(公告)日：2012-12-06

    申请号：PCT/CN2011/082111

    申请日：2011-11-11

    Applicant: TSINGHUA UNIVERSITY ,  WANG, Jing ,  GUO, Lei

    Inventor： WANG, Jing ,  GUO, Lei

    IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

    CPC classification number: H01L29/7842 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02587 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/3247 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0688 ,  H01L29/1054 ,  H01L29/151 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/78

    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (1100); a plurality of convex structures (1200) formed on the substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures (1200) is less than 50nm in width; a plurality of floated films (1300), in which the floated films (1300) are partitioned into a plurality of sets, a channel layer is formed on a convex structure (1200) between the floated films (1300) in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and the cavity between the every two adjacent convex structures (1200) is filled with an insulating material (2000); and a gate stack (1400) formed on each channel layer.

    Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括：衬底（1100）; 形成在所述基板（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）以预定图案被空腔隔开，并且每两个相邻的凸起结构（1200）之间的空腔较小 宽50nm; 多个浮动膜（1300），其中浮动膜（1300）被分成多个组，在每组中的浮动膜（1300）之间的凸形结构（1200）上形成沟道层，源 区域和漏极区域分别形成在沟道层的两侧，并且每两个相邻凸起结构（1200）之间的空腔填充有绝缘材料（2000）; 和形成在每个沟道层上的栅叠层（1400）。

    HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN
    10.
    发明申请
    HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN 审中-公开
    使用稀释漏水的高压晶体管

    公开(公告)号：WO2011160041A2

    公开(公告)日：2011-12-22

    申请号：PCT/US2011/040916

    申请日：2011-06-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED ,  HAO, Ping ,  PENDHARKAR, Sameer ,  HU, Binghua ,  WANG, Qingfeng

    Inventor： HAO, Ping ,  PENDHARKAR, Sameer ,  HU, Binghua ,  WANG, Qingfeng

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

    Abstract: An integrated circuit containing an extended drain MOS transistor (100) may be formed by forming a drift region implant mask (114) with mask fingers (116) abutting a channel region (108) and extending to the source/channel active area (112), but not extending to a drain contact active area (112). Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

    Abstract translation: 可以通过形成具有与通道区域（108）邻接并延伸到源极/沟道有源区域（112）的掩模指（116）的漂移区域注入掩模（114）形成包含扩展漏极MOS晶体管（100）的集成电路， ，但不延伸到漏极接触有源区域（112）。 通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。 栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。 在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。 在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

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