公开(公告)号：WO2006135658A3

公开(公告)日：2009-04-23

申请号：PCT/US2006022220

申请日：2006-06-07

Applicant: ATMEL CORP ,  BEDARIDA LORENZO ,  SACCO ANDREA ,  ODDONE GIORGIO ,  BARTOLI SIMONE

Inventor： BEDARIDA LORENZO ,  SACCO ANDREA ,  ODDONE GIORGIO ,  BARTOLI SIMONE

IPC: G11C16/04

CPC classification number: G11C16/26

Abstract: A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.

Abstract translation: 用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。 存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。 参考矩阵耦合到存储器矩阵并具有参考单元。 逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

公开(公告)号：WO2008057835A3

公开(公告)日：2009-03-12

申请号：PCT/US2007082875

申请日：2007-10-29

Applicant: ATMEL CORP ,  FRULIO MASSIMILIANO ,  SURICO STEFANO ,  SACCO ANDREA ,  MANFRE DAVIDE

Inventor： FRULIO MASSIMILIANO ,  SURICO STEFANO ,  SACCO ANDREA ,  MANFRE DAVIDE

IPC: G11C8/00

CPC classification number: G11C16/08

Abstract: A plurality of memory sub-arrays (302A - 302X) are formed in a p-well region (304). Each of the memory sub-arrays (302A - 302X) has at least one first-level column decoder (306A - 306X) that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder (316) is formed outside of the p-well region (304) and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers (320). During a memory erase mode of operation, a high voltage is provided to bias the p-well region (304) and a plurality of high-voltage switches (326A - 326X) are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders (306 A 306X).

Abstract translation: 多个存储器子阵列（302A-302X）形成在p阱区域（304）中。 每个存储子阵列（302A-302X）具有至少一个第一级解码器（306A-306X），其包括也形成在p阱内的多个低压MOS选择晶体管。 最后一级解码器（316）形成在p阱区域（304）的外部，并且包括高压MOS晶体管，以向读出放大器（320）阵列之一提供输出信号。 在存储器擦除操作模式期间，提供高电压以偏置p阱区域（304），并且激活多个高压开关（326A-326X）以向选择器晶体管的栅极端提供高电压 在第一级列解码器（306A 306X）中。

公开(公告)号：WO2006135658A2

公开(公告)日：2006-12-21

申请号：PCT/US2006/022220

申请日：2006-06-07

Applicant: ATMEL CORPORATION ,  BEDARIDA, Lorenzo ,  SACCO, Andrea ,  ODDONE, Giorgio ,  BARTOLI, Simone

Inventor： BEDARIDA, Lorenzo ,  SACCO, Andrea ,  ODDONE, Giorgio ,  BARTOLI, Simone

IPC: G11C16/04

CPC classification number: G11C16/26

Abstract: A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.

Abstract translation: 用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。 存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。 参考矩阵耦合到存储器矩阵并具有参考单元。 逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

公开(公告)号：WO2008076553A3

公开(公告)日：2009-01-22

申请号：PCT/US2007084460

申请日：2007-11-12

Applicant: ATMEL CORP ,  BARTOLI SIMONE ,  SURICO STEFANO ,  SACCO ANDREA ,  MOSTOLA MARIA

Inventor： BARTOLI SIMONE ,  SURICO STEFANO ,  SACCO ANDREA ,  MOSTOLA MARIA

IPC: G06F11/00

CPC classification number: G11C29/82 ,  G11C29/806 ,  G11C29/846

Abstract: A redundant memory array (300) has r columns of redundant memory cells (306), r redundant senses (312), and a redundant column decoder (308). Redundant address registers (332) store addresses of defective regular memory cells. Redundant latches (338) are provided in n groups of r latches. Redundancy comparison logic (330) compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal (333) to disable the regular senses (310) for one of the n groups of m columns, an ENABLE_LATCH signal (334) to one of the n groups of m columns to disable corresponding regular senses, and one of r REDO signals (336) to a respective one of the r redundant latches (338) in one of the n groups that is disabled. The selected one of the redundant latches (338) activates one of the r redundant senses (312) to access a redundant column.

Abstract translation: 冗余存储器阵列（300）具有r列的冗余存储器单元（306），r冗余感测（312）和冗余列解码器（308）。 冗余地址寄存器（332）存储有缺陷的常规存储单元的地址。 冗余锁存器（338）设置在n组r个锁存器中。 冗余比较逻辑（330）将缺陷规则存储器单元的地址与外部输入地址进行比较。 如果比较是真实的，则提供的是：禁用n列m列中的一个的常规感测（310）的DISABLE_LOAD信号（333），到m列的n组之一的ENABLE_LATCH信号（334） 禁用相应的常规感测，并且将r个REDO信号中的一个（336）禁止到被禁用的n个组中的一个中的r个冗余锁存器（338）中的相应一个。 所选择的冗余锁存器（338）中的一个激活r个冗余感测（312）中的一个以访问冗余列。

公开(公告)号：WO2006044163A2

公开(公告)日：2006-04-27

申请号：PCT/US2005/035166

申请日：2005-10-03

Applicant: ATMEL CORPORATION ,  FRULIO, Massimiliano ,  RIVA REGGIORI, Riccardo ,  SACCO, Andrea ,  FIGINI, Luca

Inventor： FRULIO, Massimiliano ,  RIVA REGGIORI, Riccardo ,  SACCO, Andrea ,  FIGINI, Luca

IPC: G11C16/06

CPC classification number: G11C16/26

Abstract: A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.

Abstract translation: 一种用于避免偏移并减小具有多个存储器组电路的非易失性存储器的占位面积的系统和方法。 每个存储体电路具有耦合到读出放大器，耦合到存储器单元的行和列解码器以及耦合到读出放大器的偏置电路的存储单元。 该系统包括耦合到多个存储体电路中的每一个的参考单元矩阵。 参考单元矩阵被配置为为多个存储体电路中的每一个提供参考单元电流。

公开(公告)号：WO2004077439A3

公开(公告)日：2004-12-29

申请号：PCT/US2004004729

申请日：2004-02-17

Applicant: ATMEL CORP ,  BEDARIDA LORENZO ,  SACCO ANDREA ,  MARZIANI MONICA

Inventor： BEDARIDA LORENZO ,  SACCO ANDREA ,  MARZIANI MONICA

IPC: G11C7/06 ,  G11C7/14 ,  G11C16/28 ,  G11C11/34

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/14 ,  G11C2207/063 ,  G11C2207/2254

Abstract: A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.

Abstract translation: 一种用于闪存的可配置的镜像放大器系统，具有以下特征。 电源产生参考电压。 多个晶体管被偏置在参考电压。 多个晶体管各自耦合到第二晶体管。 多个晶体管中的每一个也被配置为提供用于与闪速存储器进行比较的电流。 参考电压是内部的，稳定的，独立于电源或温度的变化。 多个晶体管彼此并联。 反射镜晶体管耦合到多个晶体管。 多个晶体管被配置为使得至少一个晶体管中的至少一个被激活，以便提供用于与闪存相比较的电流。 此外，可以修改参考电压以便修改用于与闪存存储器进行比较的电流。

公开(公告)号：WO2008076553A2

公开(公告)日：2008-06-26

申请号：PCT/US2007/084460

申请日：2007-11-12

Applicant: ATMEL CORPORATION ,  BARTOLI, Simone ,  SURICO, Stefano ,  SACCO, Andrea ,  MOSTOLA, Maria

Inventor： BARTOLI, Simone ,  SURICO, Stefano ,  SACCO, Andrea ,  MOSTOLA, Maria

IPC: G11C16/06

CPC classification number: G11C29/82 ,  G11C29/806 ,  G11C29/846

Abstract: A redundant memory array (300) has r columns of redundant memory cells (306), r redundant senses (312), and a redundant column decoder (308). Redundant address registers (332) store addresses of defective regular memory cells. Redundant latches (338) are provided in n groups of r latches. Redundancy comparison logic (330) compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal (333) to disable the regular senses (310) for one of the n groups of m columns, an ENABLE_LATCH signal (334) to one of the n groups of m columns to disable corresponding regular senses, and one of r REDO signals (336) to a respective one of the r redundant latches (338) in one of the n groups that is disabled. The selected one of the redundant latches (338) activates one of the r redundant senses (312) to access a redundant column.

Abstract translation: 冗余存储器阵列（300）具有r列的冗余存储器单元（306），r冗余感测（312）和冗余列解码器（308）。 冗余地址寄存器（332）存储有缺陷的常规存储单元的地址。 冗余锁存器（338）设置在n组r个锁存器中。 冗余比较逻辑（330）将缺陷规则存储器单元的地址与外部输入地址进行比较。 如果比较是真实的，则提供的是：禁用n列m列中的一个的常规感测（310）的DISABLE_LOAD信号（333），到m列的n组之一的ENABLE_LATCH信号（334） 禁用相应的常规感测，并且将r个REDO信号中的一个（336）禁止到被禁用的n个组中的一个中的r个冗余锁存器（338）中的相应一个。 所选择的冗余锁存器（338）中的一个激活r个冗余感测（312）中的一个以访问冗余列。

公开(公告)号：WO2008057835A2

公开(公告)日：2008-05-15

申请号：PCT/US2007/082875

申请日：2007-10-29

Applicant: ATMEL CORPORATION ,  FRULIO, Massimiliano ,  SURICO, Stefano ,  SACCO, Andrea ,  MANFRE, Davide

Inventor： FRULIO, Massimiliano ,  SURICO, Stefano ,  SACCO, Andrea ,  MANFRE, Davide

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/08

Abstract: A plurality of memory sub-arrays (302A - 302X) are formed in a p-well region (304). Each of the memory sub-arrays (302A - 302X) has at least one first-level column decoder (306A - 306X) that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder (316) is formed outside of the p-well region (304) and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers (320). During a memory erase mode of operation, a high voltage is provided to bias the p-well region (304) and a plurality of high-voltage switches (326A - 326X) are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders (306A - 306X). One or more intermediate-level column decoders (312) are formed as low-voltage selector transistors in the p-well (304) between the first-level column decoder (306A - 306X) and the last-level column decoder (316). Each of the intermediate- level column decoders (312) also has a high-voltage switch (326Y) that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate- level column decoders (312).

Abstract translation: 多个存储器子阵列（302A-302X）形成在p阱区域（304）中。 每个存储子阵列（302A-302X）具有至少一个第一级解码器（306A-306X），其包括也形成在p阱内的多个低压MOS选择晶体管。 最后一级解码器（316）形成在p阱区域（304）的外部，并且包括高压MOS晶体管，以向读出放大器（320）阵列之一提供输出信号。 在存储器擦除操作模式期间，提供高电压以偏置p阱区域（304），并且激活多个高压开关（326A-326X）以向选择器晶体管的栅极端提供高电压 在第一级列解码器（306A-306X）中。 在第一级列解码器（306A-306X）和最后级列解码器（316）之间的p阱（304）中形成一个或多个中间级列解码器（312）作为低电压选择晶体管。 每个中间级列解码器（312）还具有在存储器擦除操作模式期间被激活以向中间级列解码器（312）的栅极端提供高电压的高压开关（326Y）。

公开(公告)号：WO2008045411A2

公开(公告)日：2008-04-17

申请号：PCT/US2007/021534

申请日：2007-10-09

Applicant: ATMEL CORPORATION ,  PASSERINI, Marco ,  SIVERO, Stefano ,  SACCO, Andrea ,  MARZIANI, Monica

Inventor： PASSERINI, Marco ,  SIVERO, Stefano ,  SACCO, Andrea ,  MARZIANI, Monica

IPC: G11C5/14 ,  G11C16/04 ,  G11C7/00 ,  G11C7/02 ,  G11C11/34

CPC classification number: G11C7/02 ,  G11C5/145

Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.

Abstract translation: 公开了一种改善电子设备性能的装置和方法。 当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。 空闲状态减少了由于线路或节点中突然的电压变化引起的开关扰动的不良影响。

公开(公告)号：WO2006058134A3

公开(公告)日：2006-06-01

申请号：PCT/US2005/042570

申请日：2005-11-23

Applicant: ATMEL CORPORATION ,  FRULIO, Massimiliano ,  BARTOLI, Simone ,  MANFRÉ, David ,  SACCO, Andrea

Inventor： FRULIO, Massimiliano ,  BARTOLI, Simone ,  MANFRÉ, David ,  SACCO, Andrea

IPC: G11C16/04

Abstract: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.