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    OPTICAL MODULATOR FROM STANDARD FABRICATION PROCESSING
    1.
    发明申请
    OPTICAL MODULATOR FROM STANDARD FABRICATION PROCESSING 审中-公开
    标准制造加工的光学调制器

    公开(公告)号：WO2014201286A1

    公开(公告)日：2014-12-18

    申请号：PCT/US2014/042177

    申请日：2014-06-12

    Applicant: POPOVIC, Milos A. ,  SHAINLINE, Jeffrey Michael ,  ORCUTT, Jason ,  STOJANOVIC, Vladimir Marko

    Inventor： POPOVIC, Milos A. ,  SHAINLINE, Jeffrey Michael ,  ORCUTT, Jason ,  STOJANOVIC, Vladimir Marko

    IPC: G02F1/025

    CPC classification number: G02F1/2257 ,  G02B6/29338 ,  G02B6/2938 ,  G02B6/29395 ,  G02F1/025 ,  G02F2001/3509 ,  G02F2201/17 ,  G02F2203/05 ,  G02F2203/07 ,  G02F2203/15

    Abstract: An optical modulator is disclosed that includes an optical resonator structure. The optical resonator structure includes at least one non-linear portion, the at least one non-linear portion comprising at least one radial junction region. The at least one radial junction region is formed between at least first and second materials, respectively, having different electronic conductivity characteristics. A principal axis of the at least one radial junction region is oriented along a radius of curvature of the at least one non-linear portion. The optical modulator includes an optical waveguide that is coupled to the at least one non-linear portion of the optical resonator structure.

    Abstract translation: 公开了一种包括光谐振器结构的光调制器。 所述光学谐振器结构包括至少一个非线性部分，所述至少一个非线性部分包括至少一个径向接合区域。 所述至少一个径向结区域分别形成在具有不同电子导电特性的至少第一和第二材料之间。 所述至少一个径向接合区域的主轴线沿所述至少一个非线性部分的曲率半径定向。 光调制器包括耦合到光谐振器结构的至少一个非线性部分的光波导。

    DATA-LEVEL CLOCK RECOVERY
    2.
    发明申请
    DATA-LEVEL CLOCK RECOVERY 审中-公开
    数据级时钟恢复

    公开(公告)号：WO2005029743A2

    公开(公告)日：2005-03-31

    申请号：PCT/US2004/029347

    申请日：2004-09-08

    Applicant: RAMBUS INC. ,  STOJANOVIC, Vladimir, M.

    Inventor： STOJANOVIC, Vladimir, M.

    IPC: H04L

    CPC classification number: H04L7/0331 ,  H04L7/0087 ,  H04L7/0334 ,  H04L7/0337

    Abstract: A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a first threshold. An second sampling circuit generates an error sample in response to one of the transitions of the clock signal, the error sample having either the first state or the second state according to whether the incoming signal exceeds a second threshold. A phase adjust circuit adjusts the phase of the clock signal if the sequence of data samples matches a predetermined pattern and based, at least in part, on whether the error sample has the first state or the second state.

    Abstract translation: 用于调整时钟信号相位的电路。 第一采样电路响应于时钟信号的转变而生成数据样本序列，根据输入信号是否超过第一阈值，每个数据样本具有第一状态或第二状态。 第二采样电路根据输入信号是否超过第二阈值，响应于时钟信号的转换之一产生误差采样，该误差采样具有第一状态或第二状态。 如果数据样本序列与预定模式匹配并且至少部分地基于该误差样本是否具有第一状态或第二状态，则相位调整电路调整时钟信号的相位。

    LINEAR TRANSFORMATION CIRCUITS
    5.
    发明申请
    LINEAR TRANSFORMATION CIRCUITS 审中-公开
    线性变换电路

    公开(公告)号：WO2007024446A2

    公开(公告)日：2007-03-01

    申请号：PCT/US2006/030411

    申请日：2006-08-02

    Applicant: RAMBUS INC. ,  AMIRKHANY, Amir ,  STOJANOVIC, Vladimir, M. ,  ALON, Elad ,  ZERBE, Jared, L. ,  HOROWITZ, Mark, A.

    Inventor： AMIRKHANY, Amir ,  STOJANOVIC, Vladimir, M. ,  ALON, Elad ,  ZERBE, Jared, L. ,  HOROWITZ, Mark, A.

    IPC: G06F17/14

    CPC classification number: G06F17/141 ,  G06J1/005

    Abstract: A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.

    Abstract translation: 变换电路包括第一电路和第二电路。 第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。 第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。 每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。 第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。 每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

    MARGIN TEST METHODS AND CIRCUITS
    6.
    发明申请
    MARGIN TEST METHODS AND CIRCUITS 审中-公开
    测量方法和电路

    公开(公告)号：WO2004105334A3

    公开(公告)日：2005-06-02

    申请号：PCT/US2004015895

    申请日：2004-05-20

    Applicant: RAMBUS INC ,  GARLEPP BRUNO W ,  CHEN FRED F ,  HO ANDREW ,  STOJANOVIC VLADIMIR

    Inventor： GARLEPP BRUNO W ,  CHEN FRED F ,  HO ANDREW ,  STOJANOVIC VLADIMIR

    IPC: H04L1/20 ,  H04L1/24 ,  H04L25/03

    CPC classification number: H04L25/03006 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242

    Abstract: Described are methods and circuits for margin testing digital receivers. Some embodiments prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing, while other embodiments rely upon the statistics of sampled data to explore the margin characteristics of received data.

    Abstract translation: 描述了数字接收机边缘测试的方法和电路。 一些实施例可以防止误差响应于错误接收的数据而崩溃，并且因此可用于采用历史数据的接收机中以减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例对误差数据进行滤波以便于特定于图案的边缘测试，而其他实施例依赖于采样数据的统计来探索接收数据的边缘特性。

    MARGIN TEST METHODS AND CIRCUITS
    7.
    发明申请
    MARGIN TEST METHODS AND CIRCUITS 审中-公开
    测量方法和电路

    公开(公告)号：WO2004105334A2

    公开(公告)日：2004-12-02

    申请号：PCT/US2004/015895

    申请日：2004-05-20

    Applicant: RAMBUS INC. ,  GARLEPP, Bruno, W. ,  CHEN, Fred, F. ,  HO, Andrew ,  STOJANOVIC, Vladimir

    Inventor： GARLEPP, Bruno, W. ,  CHEN, Fred, F. ,  HO, Andrew ,  STOJANOVIC, Vladimir

    IPC: H04L25/00

    CPC classification number: H04L25/03006 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242

    Abstract: Described are methods and circuits for margin testing digital receivers. Some embodiments prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing, while other embodiments rely upon the statistics of sampled data to explore the margin characteristics of received data.

    Abstract translation: 描述了数字接收机边缘测试的方法和电路。 一些实施例可以防止误差响应于错误接收的数据而崩溃，并且因此可用于采用历史数据的接收机中以减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例对误差数据进行滤波以便于特定于图案的边缘测试，而其他实施例依赖于采样数据的统计来探索接收到的数据的边缘特性。

    LINEAR TRANSFORMATION CIRCUIT
    9.
    发明申请
    LINEAR TRANSFORMATION CIRCUIT 审中-公开
    线性变换电路

    公开(公告)号：WO2007076229A2

    公开(公告)日：2007-07-05

    申请号：PCT/US2006061655

    申请日：2006-12-06

    Applicant: RAMBUS INC ,  ABBASFAR ALIAZAM ,  AMIRKHANY AMIR ,  STOJANOVIC VLADIMIR ,  HOROWITZ MARK A

    Inventor： ABBASFAR ALIAZAM ,  AMIRKHANY AMIR ,  STOJANOVIC VLADIMIR ,  HOROWITZ MARK A

    CPC classification number: G06J1/00

    Abstract: A first device is described. The first device may include a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit may have an input to receive a vector having N digital values and an output to output N first output signals, a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H, and a conversion (DAC) circuit coupled to the sign-adjustment circuit. Outputs from the DAC circuit may be summed to produce an output.

    Abstract translation: 描述第一设备。 第一装置可以包括线性变换电路以实现矩阵D的乘法。线性变换电路可以具有用于接收具有N个数字值的矢量的输入和用于输出N个第一输出信号的输出，用于调整的符号调整电路 根据一组系数H包括N个第一输出信号中的至少M个的子集的符号，以及耦合到符号调整电路的转换（DAC）电路。 来自DAC电路的输出可以相加以产生输出。

    SIGNALING SYSTEM WITH DATA CORRELATION DETECTION
    10.
    发明申请
    SIGNALING SYSTEM WITH DATA CORRELATION DETECTION 审中-公开
    具有数据相关性检测的信号发送系统

    公开(公告)号：WO2007024815A3

    公开(公告)日：2007-04-19

    申请号：PCT/US2006032687

    申请日：2006-08-21

    Applicant: RAMBUS INC ,  STOJANOVIC VLADIMIR M ,  HO ANDREW ,  CHEN FRED F ,  LI SIMON

    Inventor： STOJANOVIC VLADIMIR M ,  HO ANDREW ,  CHEN FRED F ,  LI SIMON

    IPC: H04L25/03

    CPC classification number: H04L25/03006

    Abstract: Conditionally updating equalization tap weights within an equalized signaling system based on a measure of correlation that indicates a difference between the number of received data values that have matching bits at a first pair of predetermined bit positions, and the number of received data values that have non-matching bits at the first pair of predetermined bit positions.

    Abstract translation: 基于指示在第一对预定比特位置处具有匹配比特的接收数据值的数量与具有非接收数据值的接收数据值的数量之间的差的相关性度量，在均衡信令系统内有条件地更新均衡抽头权重 在第一对预定比特位置上匹配比特。

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