公开(公告)号：WO2009070532A1

公开(公告)日：2009-06-04

申请号：PCT/US2008/084541

申请日：2008-11-24

Applicant: APPLIED MATERIALS, INC. ,  BORDEN, Peter ,  TAYLOR, Mitchell C.

Inventor： BORDEN, Peter ,  TAYLOR, Mitchell C.

IPC: H01L21/00 ,  H01L31/06

CPC classification number: H01L31/18 ,  H01L31/022425 ,  Y02E10/50

Abstract: A method for forming a selective emitter on a silicon solar cell is provided. In one embodiment, the method comprises forming an oxide layer on a surface of a P-type silicon substrate, implanting phosphorus doping atoms into the oxide layer on the substrate using plasma immersion ion implantation, patterning the oxide layer, annealing the substrate to provide heavily doped regions in the patterned regions and a lightly doped region between the patterned regions, and providing metal contacts at the heavily doped regions.

Abstract translation: 提供了一种在硅太阳能电池上形成选择性发射极的方法。 在一个实施例中，该方法包括在P型硅衬底的表面上形成氧化物层，使用等离子体浸没离子注入将磷掺杂原子注入到衬底上的氧化物层中，图案化氧化物层，退火衬底以提供大量 图案化区域中的掺杂区域和图案化区域之间的轻掺杂区域，并且在重掺杂区域提供金属接触。

公开(公告)号：WO2011084575A2

公开(公告)日：2011-07-14

申请号：PCT/US2010/060708

申请日：2010-12-16

Applicant: APPLIED MATERIALS, INC. ,  TAYLOR, Mitchell C. ,  FELCH, Susan B.

Inventor： TAYLOR, Mitchell C. ,  FELCH, Susan B.

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/67207 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32412 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2018 ,  H01L21/2236 ,  H01L21/268 ,  H01L21/67115 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/6831 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include (a) providing a substrate having a p-type silicon region; (b) depositing a silicon seed layer atop the p-type silicon region; (c) depositing a silicon-containing bulk layer comprising silicon, silicon and a lattice adjusting element or silicon and an n-type dopant atop the silicon seed layer; (d) implanting at least one of the lattice adjusting element or the n-type dopant which is absent from the silicon-containing bulk layer deposited in (c) into the silicon-containing bulk layer; and (e) annealing the silicon-containing bulk layer with an energy beam after implantation in (d). In some embodiments, the substrate may comprise a partially fabricated NMOS transistor device having a source/drain region defined therein.

Abstract translation: 本文提供了具有受控沟道应变和结电阻的NMOS晶体管及其制造方法。 在一些实施例中，用于形成NMOS晶体管的方法可以包括（a）提供具有p型硅区域的衬底; （b）在所述p型硅区域顶上沉积硅晶种层; （c）在硅籽晶层顶上沉积包含硅，硅和晶格调整元素或硅和n型掺杂物的含硅体层; （d）将（c）中沉积的含硅体层中不存在的晶格调整元素或n型掺杂物中的至少一种注入到含硅体层中; （e）在（d）中注入后用能量束退火含硅体层。 在一些实施例中，衬底可以包括其中限定有源极/漏极区的部分制造的NMOS晶体管器件。

公开(公告)号：WO2011084575A3

公开(公告)日：2011-12-01

申请号：PCT/US2010060708

申请日：2010-12-16

Applicant: APPLIED MATERIALS INC ,  TAYLOR MITCHELL C ,  FELCH SUSAN B

Inventor： TAYLOR MITCHELL C ,  FELCH SUSAN B

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/67207 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/32412 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2018 ,  H01L21/2236 ,  H01L21/268 ,  H01L21/67115 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/6831 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include (a) providing a substrate having a p-type silicon region; (b) depositing a silicon seed layer atop the p-type silicon region; (c) depositing a silicon-containing bulk layer comprising silicon, silicon and a lattice adjusting element or silicon and an n-type dopant atop the silicon seed layer; (d) implanting at least one of the lattice adjusting element or the n-type dopant which is absent from the silicon-containing bulk layer deposited in (c) into the silicon-containing bulk layer; and (e) annealing the silicon-containing bulk layer with an energy beam after implantation in (d). In some embodiments, the substrate may comprise a partially fabricated NMOS transistor device having a source/drain region defined therein.

Abstract translation: 具有受控的通道应变和结电阻的NMOS晶体管及其制造方法在此提供。 在一些实施例中，用于形成NMOS晶体管的方法可以包括（a）提供具有p型硅区域的衬底; （b）在p型硅区域的顶部沉积硅晶种层; （c）在所述硅籽晶层的顶部沉积包含硅，硅和晶格调节元件或硅和n型掺杂剂的含硅体层; （d）将沉积在（c）中的含硅体积层中不存在的晶格调整元件或n型掺杂物中的至少一个注入到含硅体层中; 和（e）在（d）中植入之后用能量束对含硅体层进行退火。 在一些实施例中，衬底可以包括其中限定了源极/漏极区域的部分制造的NMOS晶体管器件。