公开(公告)号：WO2009046114A3

公开(公告)日：2009-05-22

申请号：PCT/US2008078460

申请日：2008-10-01

Applicant: UNIV FLORIDA ,  FOSSUM JERRY G ,  MATHEW LEO ,  SADD MICHAEL ,  TRIVEDI VISHAL P

Inventor： FOSSUM JERRY G ,  MATHEW LEO ,  SADD MICHAEL ,  TRIVEDI VISHAL P

IPC: H01L21/8242

CPC classification number: H01L27/108 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/7841 ,  H01L29/785

Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded- DRAM applications. Further embodiments pertain to a floating-body/ gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Abstract translation: 实施例涉及用于嵌入式DRAM应用的双晶体管（2T）浮体单元（FBC）。 除了更好的信号裕量，更长的数据保持时间和更高的存储器密度之外，进一步的实施例涉及浮体/栅单元（FBGC），其减小功耗。

公开(公告)号：WO2009046114A2

公开(公告)日：2009-04-09

申请号：PCT/US2008/078460

申请日：2008-10-01

Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC. ,  FOSSUM, Jerry, G. ,  MATHEW, Leo ,  SADD, Michael ,  TRIVEDI, Vishal, P.

Inventor： FOSSUM, Jerry, G. ,  MATHEW, Leo ,  SADD, Michael ,  TRIVEDI, Vishal, P.

IPC: H01L21/8242

CPC classification number: H01L27/108 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/7841 ,  H01L29/785

Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded- DRAM applications. Further embodiments pertain to a floating-body/ gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.

Abstract translation: 实施例涉及用于嵌入式DRAM应用的双晶体管（2T）浮体单元（FBC）。 除了更好的信号余量，更长的数据保持和更高的存储器密度之外，其它实施例涉及浮体/栅极单元（FBGC），其产生功率损耗的降低。

公开(公告)号：WO2008150683A1

公开(公告)日：2008-12-11

申请号：PCT/US2008/064100

申请日：2008-05-19

Applicant: FREESCALE SEMICONDUCTOR INC. ,  SPENCER, Gregory, S. ,  TRIVEDI, Vishal, P.

Inventor： SPENCER, Gregory, S. ,  TRIVEDI, Vishal, P.

IPC: H01L21/324 ,  H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/324 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a doped region (34, 32) includes, in one embodiment, implanting a dopant into a region (30, 28) in a semiconductor substrate (12), recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser (52). In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.

Abstract translation: 在一个实施例中，形成掺杂区域（34,32）的方法包括：将掺杂剂注入到半导体衬底（12）中的区域（30,28）中，通过执行第一毫秒退火对该区域进行再结晶，其中第一 毫秒退火具有第一温度和第一停留时间，并且在重结晶该区域之后使用第二毫秒退火激活该区域，其中第二毫秒退火具有第二温度和第二停留时间。 在一个实施例中，第一毫秒退火和第二毫秒退火使用激光（52）。 在一个实施例中，第一温度与第二温度相同，并且第一停留时间与第二停留时间相同。 在另一实施例中，第一温度与第二温度不同，第一停留时间不同于第二停留时间。

公开(公告)号：WO2008014032A1

公开(公告)日：2008-01-31

申请号：PCT/US2007/068098

申请日：2007-05-03

Applicant: FREESCALE SEMICONDUCTOR INC. ,  SPENCER, Gregory, S. ,  KOLAGUNTA, Venkat, R. ,  RAMANI, Narayanan, C. ,  TRIVEDI, Vishal, P.

Inventor： SPENCER, Gregory, S. ,  KOLAGUNTA, Venkat, R. ,  RAMANI, Narayanan, C. ,  TRIVEDI, Vishal, P.

IPC: H01L31/117

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6653 ,  H01L29/7843

Abstract: A strained semiconductor layer (18) is achieved by a method for transferring stress from a dielectric layer (30) to a semiconductor layer (18). The method comprises providing a substrate (12) having a semiconductor layer (18). A dielectric layer (30) having a stress is formed over the semiconductor layer (18). A radiation anneal (32) is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer (30) to create a stress in the semiconductor layer (18). The dielectric layer (30) may then be removed. At least a portion of the stress in the semiconductor layer (18) remains in the semiconductor layer after the dielectric layer (30) is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions (26, 28).

Abstract translation: 应变半导体层（18）通过用于将应力从介电层（30）传递到半导体层（18）的方法来实现。 该方法包括提供具有半导体层（18）的衬底（12）。 在半导体层（18）上形成具有应力的电介质层（30）。 辐射退火（32）施加在电介质层上，持续时间不超过10毫秒，导致电介质层（30）的应力在半导体层（18）中产生应力。 然后可以去除电介质层（30）。 在去除电介质层（30）之后，半导体层（18）中的应力的至少一部分保留在半导体层中。 辐射退火可以通过使用激光束或闪光工具。 辐射退火也可用于激活源/漏区（26,28）。