公开(公告)号：WO2015160565A1

公开(公告)日：2015-10-22

申请号：PCT/US2015/024659

申请日：2015-04-07

Applicant: 21, INC.

Inventor： PAUKER, Matthew ,  DREGO, Nigel ,  KHETERPAL, Veerbhan ,  FIRU, Daniel

IPC: G06Q20/06 ,  G06Q20/02 ,  G06Q20/36 ,  G06Q20/38

CPC classification number: G06Q20/3827 ,  G06Q20/02 ,  G06Q20/0655 ,  G06Q20/3674 ,  G06Q20/3678 ,  G06Q20/3829 ,  G06Q20/401 ,  G06Q2220/00 ,  H04L9/3242 ,  H04L2209/56

Abstract: Mining circuitry may be used to mine digital currency such as bitcoins by computing solutions to a cryptographic puzzle. Successful computation of a solution to the cryptographic puzzle may provide a reward of the digital currency. The mining circuitry may partition the mined reward between a first digital wallet and a second digital wallet. The first digital wallet may be user-provided, whereas the second digital wallet may be hardcoded into the dedicated mining circuitry. The mining circuitry may include control circuitry and multiple processing core circuits. The control circuitry may control the processing cores to solve the cryptographic puzzle via exhaustive search over possible inputs to the cryptographic puzzle.

Abstract translation: 采矿电路可用于通过计算解密到拼图的解决方案来挖掘诸如比特币的数字货币。 对密码拼图的解决方案的成功计算可以提供数字货币的奖励。 采矿电路可以在第一数字钱包和第二数字钱包之间划分开采奖励。 第一数字钱包可以是用户提供的，而第二数字钱包可以被硬编码到专用挖掘电路中。 采矿电路可以包括控制电路和多个处理核心电路。 控制电路可以控制处理核心，以通过对可能的加密拼图的输入进行穷举搜索来解决密码拼图。

公开(公告)号：WO2016069243A1

公开(公告)日：2016-05-06

申请号：PCT/US2015/054895

申请日：2015-10-09

Applicant: 21, INC.

Inventor： KHETERPAL, Veerbhan ,  FIRU, Daniel ,  DREGO, Nigel

IPC: G06Q20/36 ,  G06Q40/04 ,  G06Q20/38 ,  H04L9/06

CPC classification number: G06F17/30539 ,  G06F17/30864 ,  G06Q20/06 ,  G06Q20/3678 ,  G06Q20/3827 ,  G06Q40/04 ,  H04L9/0643 ,  H04L9/3236 ,  H04L2209/30 ,  H04L2209/38

Abstract: An integrated circuit may be provided with cryptocurrency mining capabilities. The integrated circuit may include control circuitry and a number of processing cores that complete a Secure Hash Algorithm 256 (SHA-256) function in parallel. Logic circuitry may be shared between multiple processing cores. Each processing core may perform sequential rounds of cryptographic hashing operations based on a hash input and message word inputs. The control circuitry may control the processing cores to complete the SHA-256 function over different search spaces. The shared logic circuitry may perform a subset of the sequential rounds for multiple processing cores. If desired, the shared logic circuitry may generate message word inputs for some of the sequential rounds across multiple processing cores. By sharing logic circuitry across cores, chip area consumption and power efficiency may be improved relative to scenarios where the cores are formed using only dedicated logic.

Abstract translation: 集成电路可以提供密码学挖掘功能。 集成电路可以包括并行地完成安全散列算法256（SHA-256）功能的控制电路和多个处理核心。 逻辑电路可以在多个处理核之间共享。 每个处理核心可以基于散列输入和消息字输入来执行连续循环的加密散列操作。 控制电路可以控制处理核心以在不同的搜索空间上完成SHA-256功能。 共享逻辑电路可以执行多个处理核的顺序循环的子集。 如果需要，共享逻辑电路可以跨多个处理核心的一些顺序循环产生消息字输入。 通过跨核心共享逻辑电路，相对于仅使用专用逻辑形成核心的情况，可以提高芯片面积消耗和功率效率。

公开(公告)号：WO2016060931A1

公开(公告)日：2016-04-21

申请号：PCT/US2015/054708

申请日：2015-10-08

Applicant: 21, INC.

Inventor： KHETERPAL, Veerbhan ,  FIRU, Daniel ,  DREGO, Nigel

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/62

Abstract: Circuit design equipment may design logic for a circuit. The design equipment may discover optimized design constraints and an optimized clock signal frequency for the circuit. The design equipment may output the discovered optimized clock signal frequency and design constraints to circuit fabrication equipment for fabricating the corresponding circuit. The design equipment may discover the optimized clock signal frequency and design constraints by populating a cost function with different clock signal frequencies and different design constraint values. The cost function may be, for example, a multi-dimensional surface. The design equipment may identify a global minimum of the cost function and may identify the clock signal frequency and design constraint values that correspond to the global minimum as the optimized clock frequency and optimized design constraints to provide to circuit fabrication equipment. The fabrication equipment may fabricate the circuit to implement the optimized design constraint values and clock frequency.

Abstract translation: 电路设计设备可以为电路设计逻辑。 设计设备可能会发现电路的优化设计约束和优化的时钟信号频率。 设计设备可以将发现的优化时钟信号频率和设计约束输出到用于制造相应电路的电路制造设备。 设计设备可以通过填充具有不同时钟信号频率和不同设计约束值的成本函数来发现优化的时钟信号频率和设计约束。 成本函数可以是例如多维表面。 设计设备可以识别成本函数的全局最小值，并且可以将对应于全局最小值的时钟信号频率和设计约束值识别为优化的时钟频率和为电路制造设备提供的优化设计约束。 制造设备可以制造电路以实现优化的设计约束值和时钟频率。

公开(公告)号：WO2016060932A1

公开(公告)日：2016-04-21

申请号：PCT/US2015/054711

申请日：2015-10-08

Applicant: 21, INC

Inventor： KHETERPAL, Veerbhan ,  FIRU, Daniel ,  DREGO, Nigel

IPC: H04L9/06

CPC classification number: H04L9/3242 ,  G06F9/30098 ,  H04L9/0643 ,  H04L2209/125 ,  H04L2209/20 ,  H04L2209/24 ,  H04L2209/30 ,  H04L2209/38 ,  H04L2209/56

Abstract: Cryptographic hashing circuitry such as mining circuitry used to mine digital currency may be formed on an integrated circuit. The hashing circuitry may include sequential rounds of register and logic circuitry that perform operations of a cryptographic protocol. A final hash value output by the hashing circuitry may include hash values stored at previous rounds of the cryptographic hashing circuitry. The hashing circuitry may be formed with only two registers per round, thereby optimizing chip area consumption. The hashing circuitry may perform sequential rounds of cryptographic hashing based on an initial hash value and multiple message words. One or more message registers may store the message words. Control circuitry may selectively route the message words from the message register to the hashing circuitry using pointers. If desired, the message registers may be replaced by one or more arrays of memory elements read using row and column pointers.

Abstract translation: 可以在集成电路上形成诸如用于挖掘数字货币的采矿电路的加密散列电路。 散列电路可以包括执行密码协议的操作的顺序循环的寄存器和逻辑电路。 由哈希电路输出的最终哈希值可以包括在密码散列电路的前几轮存储的散列值。 散列电路可以每轮形成两个寄存器，从而优化芯片面积消耗。 散列电路可以基于初始哈希值和多个消息字来执行连续的加密散列。 一个或多个消息寄存器可以存储消息字。 控制电路可以使用指针来选择性地将消息字从消息寄存器路由到散列电路。 如果需要，消息寄存器可以由使用行和列指针读取的一个或多个存储器元件阵列替代。

公开(公告)号：WO2016060930A1

公开(公告)日：2016-04-21

申请号：PCT/US2015/054706

申请日：2015-10-08

Applicant: 21, INC.

Inventor： FIRU, Daniel ,  KHETERPAL, Veerbhan ,  DREGO, Nigel

IPC: H04L9/06

CPC classification number: G05B19/045 ,  H03K3/356 ,  H03K19/0016 ,  H04L9/0643 ,  H04L2209/12 ,  H04L2209/56

Abstract: Digital systems formed on integrated circuits may include sequential logic circuitry (22). The sequential logic circuitry (22) may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit (24-1) and a second latching circuit (24-2) that each latch bits (SO", SI') onto their respective outputs when clocked at different levels (Clk: high, low). The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit (30-1) interposed between the first and second latching circuits generates a second bit (SI') based on at least the first bit (SO"). The first and second bits (SO", SI') may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuity (30-1, 30-2) on two sides of a given latching circuit (24-1 to 24-4), dynamic power consumption by the sequential logic circuitry may be optimized.

Abstract translation: 在集成电路上形成的数字系统可以包括顺序逻辑电路（22）。 顺序逻辑电路（22）可以形成记录不同逻辑状态的有限状态机的至少一部分。 顺序逻辑电路可以包括第一锁存电路（24-1）和第二锁存电路（24-2），当在不同电平（Clk：高电平）时钟时，每个锁存位（SO“，SI'）到它们各自的输出上， 第一锁存电路可以输出第一位，组合逻辑电路可以分布在第一锁存电路的两侧，使得介于第一和第二锁存电路之间的组合逻辑电路（30-1）产生第二位 （SI“）至少基于第一位（SO”）。 第一和第二位（SO“，SI”）可以记录顺序逻辑电路的两个可能的有限逻辑状态中的一个，通过在给定的锁存电路的两侧分配组合逻辑电路（30-1,30-2） 24-1至24-4），可以优化顺序逻辑电路的动态功耗。