公开(公告)号：WO2022066542A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/051009

申请日：2021-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： APTE, Amit ,  BALAKRISHNAN, Ganesh ,  LING, Ann ,  KALYANASUNDHARAM, Vydhyanathan

IPC: G06F12/0831

Abstract: Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.

公开(公告)号：WO2022066538A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/050980

申请日：2021-09-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BHARGAVA, Ravindra ,  BALAKRISHNAN, Ganesh ,  SARGUNARAJ, Joe ,  PATEL, Chintan ,  BALAIAH ASWATHAIYA, Girish ,  KALYANASUNDHARAM, Vydhyanathan

IPC: G06F12/0804 ,  G06F12/0811 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/0813 ,  G06F12/0815

Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

公开(公告)号：WO2019118035A1

公开(公告)日：2019-06-20

申请号：PCT/US2018/051624

申请日：2018-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BHARGAVA, Ravindra N. ,  BALAKRISHNAN, Ganesh

IPC: G06F12/0893

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. External system memory is used as a last-level cache and includes one of a variety of types of dynamic random access memory (DRAM). A memory controller generates a tag request and a separate data request based on a same, single received memory request. The sending of the tag request is prioritized over sending the data request. A partial tag comparison is performed during processing of the tag request. If a tag miss is detected for the partial tag comparison, then the data request is cancelled, and the memory request is sent to main memory. If one or more tag hits are detected for the partial tag comparison, then processing of the data request is dependent upon the result of the full tag comparison.

公开(公告)号：WO2019118037A1

公开(公告)日：2019-06-20

申请号：PCT/US2018/051756

申请日：2018-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： APTE, Amit P. ,  BALAKRISHNAN, Ganesh ,  KALYANASUNDHARAM, Vydhyanathan ,  LEPAK, Kevin M.

IPC: G06F12/0817

Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.

公开(公告)号：WO2022066543A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/051010

申请日：2021-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： APTE, Amit ,  BALAKRISHNAN, Ganesh

IPC: G06F12/02 ,  G06F12/0811 ,  G06F12/0817

Abstract: Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.

公开(公告)号：WO2020055752A1

公开(公告)日：2020-03-19

申请号：PCT/US2019/050218

申请日：2019-09-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KALYANASUNDHARAM, Vydhyanathan ,  APTE, Amit P. ,  BALAKRISHNAN, Ganesh

IPC: G06F12/0817 ,  G06F12/0831

Abstract: Systems, apparatuses, and methods for accelerating accesses to private regions in a region-based cache directory scheme are disclosed. A system includes multiple processing nodes, one or more memory devices, and one or more region-based cache directories to manage cache coherence among the nodes' cache subsystems. Region-based cache directories track coherence on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. The cache directory entries for regions that are only accessed by a single node are cached locally at the node. Updates to the reference count for these entries are made locally rather than sending updates to the cache directory. When a second node accesses a first node's private region, the region is now considered shared, and the entry for this region is transferred from the first node back to the cache directory.

公开(公告)号：WO2019125559A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/051765

申请日：2018-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KALYANASUNDHARAM, Vydhyanathan ,  LEPAK, Kevin M. ,  APTE, Amit P. ,  BALAKRISHNAN, Ganesh ,  MORTON, Eric Christopher ,  COOPER, Elizabeth M. ,  BHARGAVA, Ravindra N.

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/604 ,  G06F2212/621

Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.