公开(公告)号：WO2017223346A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/038811

申请日：2017-06-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KALYANASUNDHARAM, Vydhyanathan ,  MORTON, Eric Christopher ,  APTE, Amit P. ,  COOPER, Elizabeth M.

IPC: G06F12/0813 ,  G06F12/0817 ,  G06F12/0842 ,  G06F9/52

Abstract: A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. When a home node determines a number of nodes requesting read access for a given data block assigned to the home node exceeds a threshold and a copy of the given data block is already stored at a first node of the multiple nodes in the system, the home node sends a command to the first node. The command directs the first node to forward a copy of the given data block to the home node. The home node then maintains a copy of the given data block and forwards copies of the given data block to other requesting nodes until the home node detects a write request or a lock release request for the given data block.

Abstract translation: 描述了用于多个节点之间的网络流量管理的系统和方法。 计算系统包括彼此连接的多个节点。 当归属节点确定请求对指定给归属节点的给定数据块的读取访问的节点数量超过阈值并且给定数据块的副本已经存储在系统中的多个节点中的第一节点时，家庭 节点向第一个节点发送命令。 该命令指示第一个节点将给定数据块的副本转发给主节点。 然后，主节点维护给定数据块的副本，并将给定数据块的副本转发给其他请求节点，直到主节点检测到给定数据块的写请求或锁释放请求为止。

公开(公告)号：WO2019133084A1

公开(公告)日：2019-07-04

申请号：PCT/US2018/051912

申请日：2018-09-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KALYANASUNDHARAM, Vydhyanathan ,  MORTON, Eric Christopher ,  YANG, Chen-Ping ,  APTE, Amit P. ,  COOPER, Elizabeth M.

IPC: G06F13/16 ,  G06F12/0808 ,  G06F12/0817

CPC classification number: G06F13/4282 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0824 ,  G06F13/1663 ,  G06F13/364 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Systems, apparatuses, and methods for implementing a cancel and replay mechanism for ordered requests are disclosed. A system includes at least an ordering master, a memory controller, a coherent slave coupled to the memory controller, and an interconnect fabric coupled to the ordering master and the coherent slave. The ordering master generates a write request which is forwarded to the coherent slave on the path to memory. The coherent slave sends invalidating probes to all processing nodes and then sends an indication that the write request is globally visible to the ordering master when all cached copies of the data targeted by the write request have been invalidated. In response to receiving the globally visible indication, the ordering master starts a timer. If the timer expires before all older requests have become globally visible, then the write request is cancelled and replayed to ensure forward progress in the fabric and avoid a potential deadlock scenario.

公开(公告)号：WO2020040874A1

公开(公告)日：2020-02-27

申请号：PCT/US2019/039288

申请日：2019-06-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KALYANASUNDHARAM, Vydhyanathan ,  MORTON, Eric Christopher ,  BROUSSARD, Bryan P. ,  MOYER, Paul James ,  WALKER, William Louie

IPC: G06F13/24

Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

公开(公告)号：WO2019108284A1

公开(公告)日：2019-06-06

申请号：PCT/US2018/048187

申请日：2018-08-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： MORTON, Eric Christopher ,  COOPER, Elizabeth ,  WALKER, William L. ,  HUNT, Douglas Benson ,  BORN, Richard Martin ,  LEE, Richard H. ,  MIRANDA, Paul C. ,  NG, Philip

IPC: G06F12/0815 ,  G06F12/0862

Abstract: A method for steering data for an I/O write operation (144) includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric (102), a cache (122, 123, 124, 126) as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration (156) implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data via a fetch operation (152) while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

公开(公告)号：WO2019125561A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/051782

申请日：2018-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KALYANASUNDHARAM, Vydhyanathan ,  MORTON, Eric Christopher ,  SMITH, Alan Dodson ,  CRUZ, Joe G.

IPC: H04L12/751

CPC classification number: H04L45/02 ,  G06F13/364 ,  G06F13/4022 ,  G06F13/4282 ,  G06F16/9024 ,  G06F16/9038 ,  G06F21/575 ,  G06F2213/0016 ,  H04L45/745 ,  H04L49/15 ,  H04L63/20

Abstract: A system for automatically discovering fabric topology includes at least one or more processing units, one or more memory devices, a security processor, and a communication fabric with an unknown topology coupled to the processing unit(s), memory device(s), and security processor. The security processor queries each component of the fabric to retrieve various attributes associated with the component. The security processor utilizes the retrieved attributes to create a network graph of the topology of the components within the fabric. The security processor generates routing tables from the network graph and programs the routing tables into the fabric components. Then, the fabric components utilize the routing tables to determine how to route incoming packets.

公开(公告)号：WO2019125559A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/051765

申请日：2018-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KALYANASUNDHARAM, Vydhyanathan ,  LEPAK, Kevin M. ,  APTE, Amit P. ,  BALAKRISHNAN, Ganesh ,  MORTON, Eric Christopher ,  COOPER, Elizabeth M. ,  BHARGAVA, Ravindra N.

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/128 ,  G06F2212/283 ,  G06F2212/604 ,  G06F2212/621

Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.