REMOVAL OF SURFACE DOPANTS FROM A SUBSTRATE
    3.
    发明申请
    REMOVAL OF SURFACE DOPANTS FROM A SUBSTRATE 审中-公开
    从基材上去除表面多金属

    公开(公告)号:WO2009085965A4

    公开(公告)日:2009-08-27

    申请号:PCT/US2008087446

    申请日:2008-12-18

    CPC classification number: H01L21/2254 H01L21/2253

    Abstract: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed. Substrates so treated do not form toxic compounds when stored or transported outside process equipment.

    Abstract translation: 提供了用于从掺杂衬底去除过量掺杂剂的方法和设备。 在一个实施例中,衬底通过掺杂剂的表面沉积进行掺杂,随后形成覆盖层和热扩散驱入。 向处理室提供反应性蚀刻剂混合物(具有可选等离子体)以蚀刻掉封盖层并通过与过量掺杂剂反应形成挥发性化合物。 在另一个实施例中,通过能量注入掺杂剂来掺杂衬底。 利用可选的等离子体将反应气体混合物提供给处理室,以通过与掺杂剂反应形成挥发性化合物来去除吸附在表面上的过量掺杂剂和表面附近的高浓度掺杂剂。 可以在热处理期间提供反应性气体混合物,或者可以在不同于热处理温度的温度之前或之后提供反应性气体混合物。 挥发性化合物被除去。 如此处理的基材在工艺设备外储存或运输时不会形成有毒化合物。

    SEMICONDUCTOR SUBSTRATE PROCESS USING A LOW TEMPERATURE-DEPOSITED CARBON-CONTAINING HARD MASK
    4.
    发明申请
    SEMICONDUCTOR SUBSTRATE PROCESS USING A LOW TEMPERATURE-DEPOSITED CARBON-CONTAINING HARD MASK 审中-公开
    使用低温沉积含碳硬掩模的半导体衬底工艺

    公开(公告)号:WO2007019467A2

    公开(公告)日:2007-02-15

    申请号:PCT/US2006030792

    申请日:2006-08-07

    Abstract: A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern, and depositing a carbon-containing hard mask layer on the substrate by (a) introducing a carbon-containing process gas into the chamber, (b) generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, and (c) coupling RF plasma bias power or bias voltage to the workpiece. The method further includes photolithographically defining the predetermined pattern in the carbon-containing hard mask layer, and etching the target layer in the presence of the hard mask layer.

    Abstract translation: 一种使用光学可写入掩模在半导体衬底上处理薄膜结构的方法包括:将衬底放置在反应室中,衬底在其表面上具有待按照预定图案蚀刻的目标层,并且沉积碳 - 通过(a)将含碳工艺气体引入室中,(b)在凹进路径中产生可重入的环形RF等离子体电流,所述凹进路径包括通过耦合等离子体RF源功率而覆盖工件的工艺区 到所述凹入路径的外部,以及(c)将RF等离子体偏置功率或偏置电压耦合到所述工件。 该方法还包括在含碳硬掩模层中光刻限定预定图案,并且在存在硬掩模层的情况下蚀刻目标层。

    ELECTROSTATIC CHUCK WITH SMART LIFT-PIN MECHANISM FOR PLASMA REACTOR
    6.
    发明申请
    ELECTROSTATIC CHUCK WITH SMART LIFT-PIN MECHANISM FOR PLASMA REACTOR 审中-公开
    具有用于等离子体反应器的智能引脚机构的静电卡盘

    公开(公告)号:WO2006116577A3

    公开(公告)日:2007-10-11

    申请号:PCT/US2006015971

    申请日:2006-04-26

    CPC classification number: H01L21/68742 H01L21/6831

    Abstract: A lift pin assembly for use in a reactor for processing a workpiece includes plural lift pins extending generally parallel with a lift direction, each of the plural lift pins having a top end for supporting a workpiece and a bottom end. A lift table faces the bottom ends of the pins and is translatable in a direction generally parallel with the lift direction. A small forms detector senses a force exerted by the lift pins that is sufficiently large to indicate a chucked wafer and sufficiently small to avoid dechucking a wafer A large force detector senses a force exerted by the lift pins in a range sufficient to de-chuck the wafer.

    Abstract translation: 用于处理工件的反应器中的提升销组件包括大体平行于提升方向延伸的多个提升销,多个提升销中的每一个具有用于支撑工件的顶端和底端。 升降台面向销的底端,并可在与升降方向大致平行的方向上平移。 小型检测器感测由提升销施加的力足够大以指示夹紧的晶片并且足够小以避免剥离晶片。大力检测器感测由提升销施加的力在足以脱扣的范围内 晶圆。

    COPPER BARRIER REFLOW PROCESS EMPLOYING HIGH SPEED OPTICAL ANNEALING
    7.
    发明申请
    COPPER BARRIER REFLOW PROCESS EMPLOYING HIGH SPEED OPTICAL ANNEALING 审中-公开
    采用高速光学退火的铜阻燃回流工艺

    公开(公告)号:WO2007019455A3

    公开(公告)日:2007-06-28

    申请号:PCT/US2006030746

    申请日:2006-08-07

    Abstract: A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls and depositing a metal barrier layer comprising the barrier metal on the first barrier layer. The method further includes reflowing the metal barrier layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the Line of light relative to the thin film structure in a direction transverse to the line of light.

    Abstract translation: 一种在半导体衬底上形成用于薄膜结构的阻挡层的方法包括:在具有垂直侧壁的基底层中形成高纵横比开口;在高的表面上沉积包含阻挡金属的介电化合物的介电阻挡层 包括垂直侧壁的纵横比开口以及在第一阻挡层上沉积包含阻挡金属的金属阻挡层。 该方法还包括通过以下步骤回流金属阻挡层:(a)将来自连续波激光器阵列的光引导到至少部分地延伸穿过薄膜结构的光线中,以及(b)将光线相对于薄膜 在横向于光线的方向上的薄膜结构。

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