公开(公告)号：WO2018138482A1

公开(公告)日：2018-08-02

申请号：PCT/GB2018/050185

申请日：2018-01-23

Applicant: ARM LTD

Inventor： SHIFREN, Lucian ,  REID, Kimberly Gay ,  YERIC, Gregory Munson ,  RATHOR, Manuj ,  ROSENDALE, Glen Arnold

IPC: H01L25/00 ,  H01L45/00 ,  H01L27/24

Abstract: The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters 277-283. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.

公开(公告)号：WO2019207281A1

公开(公告)日：2019-10-31

申请号：PCT/GB2019/050818

申请日：2019-03-22

Applicant: ARM LTD

Inventor： DAS, Shidhartha ,  ROSENDALE, Glen Arnold

IPC: G11C13/00 ,  G11C11/16 ,  G11C7/06 ,  G11C11/56 ,  G11C16/28

Abstract: Disclosed are methods, systems and devices for operation of memory device. A bitcell may represent a binary value, symbol, parameter or condition based on complementary impedance states of first and second memory elements. A first bitline and a second bitline may be coupled to terminals of the first and second memory elements. A circuit may detect the complementary impedance states responsive to a difference in a rates of charging of the first and second bitlines.

公开(公告)号：WO2018100372A1

公开(公告)日：2018-06-07

申请号：PCT/GB2017/053605

申请日：2017-11-29

Applicant: ARM LTD

Inventor： KUMAR, Akshay ,  AGARWAL, Piyush ,  SANDHU, Bal S. ,  ROSENDALE, Glen Arnold

IPC: H01L45/00 ,  H03M1/66

CPC classification number: H03M1/1071 ,  H01L45/04 ,  H01L45/146 ,  H03M1/1009 ,  H03M1/66 ,  H03M1/742 ,  H03M1/785 ,  H05K999/99

Abstract: The present techniques generally relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices.

公开(公告)号：WO2018206921A1

公开(公告)日：2018-11-15

申请号：PCT/GB2018/051200

申请日：2018-05-04

Applicant: ARM LTD

Inventor： BHARGAVA, Mudit ,  ROSENDALE, Glen Arnold ,  KUMAR, Akshay ,  AGARWAL, Piyush ,  DAS, Shidhartha

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0078 ,  G11C2213/74 ,  G11C2213/79

Abstract: The present techniques generally relate to correlated electron switch elements and, more particularly, to controlling current through correlated electron switch elements during programming operations.

公开(公告)号：WO2018185481A1

公开(公告)日：2018-10-11

申请号：PCT/GB2018/050908

申请日：2018-04-04

Applicant: ARM LTD

Inventor： BHARGAVA, Mudit ,  AGARWAL, Piyush ,  KUMAR, Akshay ,  ROSENDALE, Glen Arnold

IPC: G11C13/00

Abstract: The present techniques generally relate to devices, such as conducting elements, which operate to place correlated electron switch elements into first and second impedance states. In embodiments, conducting elements are maintained to be at least partially closed continuously during first and second phases of coupling the CES elements between a common source voltage and a corresponding bitline.

公开(公告)号：WO2018083447A1

公开(公告)日：2018-05-11

申请号：PCT/GB2017/053224

申请日：2017-10-25

Applicant: ARM LTD

Inventor： ROSENDALE, Glen Arnold

IPC: G11C13/00

Abstract: The present techniques generally relate to methods, systems and devices for operation of non-volatile memory devices, whereby in an embodiment,a read operation or a particular write operation may be performed on a correlated electron switch (CES) device by coupling a terminal of the CES device to a particular node through any one of multiple different resistive paths.

Abstract translation: 本技术总体上涉及用于非易失性存储器设备的操作的方法，系统和设备，由此在一个实施例中，读取操作或特定写入操作可以在相关电子开关（ CES）设备，通过将CES设备的终端通过多个不同电阻路径中的任何一个耦合到特定节点。

公开(公告)号：WO2018069716A1

公开(公告)日：2018-04-19

申请号：PCT/GB2017/053089

申请日：2017-10-12

Applicant: ARM LTD

Inventor： DAS, Shidhartha ,  BHARGAVA, Mudit ,  ROSENDALE, Glen Arnold

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one embodiment, a sense circuit may enable a determination of a current impedance state of a non-volatile memory element while avoiding an unintentional change in the state of the non-volatile memory element.

Abstract translation: 公开了用于操作非易失性存储器设备的方法，系统和设备。 在一个实施例中，感测电路可以实现确定非易失性存储器元件的当前阻抗状态，同时避免非易失性存储器元件的状态的意外变化。