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    STOCHASTIC RESET CIRCUIT
    2.
    发明申请
    STOCHASTIC RESET CIRCUIT 审中-公开
    STOCHASTIC RESET电路

    公开(公告)号：WO2007103049A2

    公开(公告)日：2007-09-13

    申请号：PCT/US2007/005011

    申请日：2007-02-26

    Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  KUTZ, Harold ,  WILLIAMS, Timothy ,  WHATELY, Morgan

    Inventor： KUTZ, Harold ,  WILLIAMS, Timothy ,  WHATELY, Morgan

    IPC: H03L7/00

    CPC classification number: G11C7/20 ,  G11C5/143 ,  G11C8/10 ,  H03K17/223 ,  H03K2217/0036

    Abstract: In one embodiment, an integrated circuit device includes a power on reset (POR) circuit (230) and a stochastic reset circuit (310) configured to control enabling and disabling of the POR circuit (230). The stochastic reset circuit (310) may have a value from among many possible values. The POR circuit (310) may be enabled during a power up sequence of the device when the value of the stochastic reset during the power up is not a value designated to allow disabling of the POR circuit (230). The stochastic reset circuit (310) may be configured such that the probability of the POR circuit (230) being disabled during the power up is extremely low. After the power up sequence, the stochastic reset circuit (310) may be controlled to allow disabling of the POR circuit (230) to conserve power.

    Abstract translation: 在一个实施例中，集成电路器件包括上电复位（POR）电路（230）和被配置为控制使能和禁止POR电路（230）的随机复位电路（310）。 随机复位电路（310）可以具有许多可能值中的值。 当上电期间随机复位的值不是指定为允许禁止POR电路（230）的值时，POR电路（310）可以在器件的上电序列期间使能。 随机复位电路（310）可以被配置为使得在加电期间POR电路（230）被禁用的概率非常低。 在上电序列之后，可以控制随机复位电路（310）以允许POR电路（230）的禁用以节省功率。

    NEGATIVE HIGH VOLTAGE HOT SWITCHING CIRCUIT
    3.
    发明申请
    NEGATIVE HIGH VOLTAGE HOT SWITCHING CIRCUIT 审中-公开
    负压高压开关电路

    公开(公告)号：WO2016200446A1

    公开(公告)日：2016-12-15

    申请号：PCT/US2016/019049

    申请日：2016-02-23

    Applicant: CYPRESS SEMICONDUCTOR CORPORATION

    Inventor： MOSCALUK, Gary ,  GEORGESCU, Bogdan ,  WILLIAMS, Timothy

    IPC: H03K17/687 ,  G11C16/02 ,  G11C16/30

    CPC classification number: H03K17/04123 ,  G11C5/147 ,  G11C5/148 ,  G11C7/1084 ,  G11C11/2297 ,  G11C11/417 ,  G11C16/30 ,  G11C17/08 ,  H03K3/356182 ,  H03K19/017 ,  H03K19/018507

    Abstract: A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.

    Abstract translation: 偏置电路包括包括第一晶体管和第二晶体管的级联晶体管。 第一晶体管的第一栅极在第一节点耦合到第二晶体管的第二栅极。 电路还包括耦合到第一晶体管或第二晶体管中的至少一个的电压控制电路。 电压控制电路被配置为根据输入信号的状态变化而改变第一晶体管或第二晶体管中的至少一个的电压电平，以允许输出信号的电压域转变，而不会使输入信号的电源信号 偏置电路。

    STATE-MONITORING MEMORY ELEMENT
    5.
    发明申请
    STATE-MONITORING MEMORY ELEMENT 审中-公开
    状态监测记忆元素

    公开(公告)号：WO2008131144A1

    公开(公告)日：2008-10-30

    申请号：PCT/US2008/060698

    申请日：2008-04-17

    Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  SHEETS, Michael ,  WILLIAMS, Timothy

    Inventor： SHEETS, Michael ,  WILLIAMS, Timothy

    IPC: G01R31/26

    CPC classification number: G11C5/14 ,  H03K19/17764

    Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the ICs state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage.

    Abstract translation: 本发明的实施例涉及一种状态监视存储元件。 状态监视存储器元件可以具有比IC上的其它常规存储器元件保持逻辑状态更低的能力。 因此，如果状态监视存储器元件在测试期间失败或失去状态，则IC状态保持可能是危险的，这可能需要IC复位。 状态监视存储元件可以通过在二极管和/或晶体管上降低对状态监视存储元件的输入电压供应来实现。 可以使用一个或多个电流源来压力状态监视存储元件。 可以使用逻辑分析器来分析状态监视存储器元件的完整性，并且响应于检测状态监视存储器元件中的故障而触发IC中的适当动作，例如复位，停止，移除电力，中断。 多个状态监视存储器元件可以分布在IC上的不同位置以获得更好的覆盖。

    PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNEL
    6.
    发明申请
    PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNEL 审中-公开
    为电容传感通道提供基线电容

    公开(公告)号：WO2016028387A1

    公开(公告)日：2016-02-25

    申请号：PCT/US2015/037615

    申请日：2015-06-25

    Applicant: CYPRESS SEMICONDUCTOR CORPORATION

    Inventor： HOSSEINI, Kaveh ,  ELLIS, Denis ,  WILLIAMS, Timothy ,  ROWE, Gabriel ,  OGIRKO, Roman ,  LAWTON, Brendan

    IPC: G06F3/041

    CPC classification number: G06F3/044 ,  G06F3/0416

    Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner may generate a baseline current using a baseline capacitor and may provide the baseline current to the channel input.

    Abstract translation: 电容感测电路可以包括与测量电容性感测阵列的单位单元的电容相关联的通道输入。 电容感测电路还可以包括耦合到通道输入的电容性硬件基础设施。 电容硬件基线设备可以使用基准电容器生成基线电流，并且可以向通道输入提供基线电流。

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