公开(公告)号：WO2003049153A2

公开(公告)日：2003-06-12

申请号：PCT/US2002/037479

申请日：2002-11-21

Applicant: HONEYWELL INTERNATIONAL INC.

Inventor： FECHNER, Paul, S.

IPC: H01L21/00

CPC classification number: H01L27/0248 ,  H02J9/061

Abstract: A semiconductor chip has first and second power supply lines and a capacitor having first and second capacitive electrodes. The first capacitive electrode is coupled to the first power supply line. A transistor has first and second current carrying electrodes and a control electrode. The first current carrying electrode is coupled to the second capacitive electrode, and the second current carrying electrode is coupled to the second power supply line. A logic controller is coupled to the second capacitive electrode and to the control electrode. The logic controller is effective to detect a defect in the capacitor and to operate the transistor so as to disconnect the capacitor from the first and second power supply lines in the event that the logic controller detects a defect in the capacitor.

Abstract translation: 半导体芯片具有第一和第二电源线以及具有第一和第二电容电极的电容器。 第一电容电极连接到第一电源线。 晶体管具有第一和第二载流电极以及控制电极。 第一载流电极连接到第二电容电极，第二载流电极连接到第二电源线。 逻辑控制器耦合到第二电容电极和控制电极。 逻辑控制器有效地检测电容器中的缺陷，并且在逻辑控制器检测到电容器中的缺陷的情况下操作晶体管以断开电容器与第一和第二电源线的连接。

公开(公告)号：WO2007133306A2

公开(公告)日：2007-11-22

申请号：PCT/US2007/002774

申请日：2007-02-01

Applicant: HONEYWELL INTERNATIONAL INC. ,  FECHNER, Paul, S. ,  SHAW, Gordon, A. ,  VOGT, Eric, E.

Inventor： FECHNER, Paul, S. ,  SHAW, Gordon, A. ,  VOGT, Eric, E.

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78615 ,  H01L29/66772

Abstract: A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie. that is shared between at least two FETs. A second trench niay also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.

Abstract translation: 一种形成身体的方法。 该方法包括在SOI工艺的STI方案期间形成体系。 在STI方案中，形成第一沟槽。 第一沟槽在SOI衬底的掩埋氧化物层之前停止。 第一个沟槽可以确定身体搭接的高度。 在至少两个FET之间共享。 第二沟槽niay也形成在第一沟槽内。 第二沟槽在SOI衬底中停止。 第二个沟槽定义了一个领带的位置和形状。 一旦定义了身体领带的位置和形状，就会在身体绑带上方沉积氧化物。 沉积的氧化物防止某些植入物进入身体束带。 通过防止这些植入物，源极和漏极注入可以与源极和漏极区域自对准，而不需要使用光致抗蚀剂掩模来屏蔽源极和漏极植入物的主体连接区域。

公开(公告)号：WO2007111665A1

公开(公告)日：2007-10-04

申请号：PCT/US2006/048405

申请日：2006-12-19

Applicant: HONEYWELL INTERNATIONAL INC. ,  VOGT, Eric, E. ,  FECHNER, Paul, S.

Inventor： VOGT, Eric, E. ,  FECHNER, Paul, S.

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L21/316

CPC classification number: H01L29/0603 ,  H01L21/02238 ,  H01L21/31662 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78654

Abstract: A method for improving mobility by bending a silicon island. Oxygen diffuses and reacts down a first axis of a pFET or nFET. This results in a partial oxidation of a buried-oxide/silicon island interface. The partial oxidation produces a thickness variation in the silicon island that creates a stress along the first axis. The stress along the first axis produces an increase in carrier mobility. Oxidation along a second, perpendicular, axis is inhibited to prevent a decrease in carrier mobility. The partial oxidation may be incorporated in SOI and STI based process flows. In addition, a dual-gate oxidation process may further enhance the observed increase in carrier mobility.

Abstract translation: 一种通过弯曲硅岛来提高移动性的方法。 氧扩散并使pFET或nFET的第一轴向下反应。 这导致掩埋氧化物/硅岛界面的部分氧化。 部分氧化产生硅岛中的厚度变化，产生沿着第一轴的应力。 沿着第一轴的应力产生载流子迁移率的增加。 抑制沿着第二垂直轴的氧化以防止载流子迁移率的降低。 部分氧化可以并入SOI和STI的工艺流程中。 此外，双栅氧化工艺可进一步增强观察到的载流子迁移率的增加。

公开(公告)号：WO2003085744A1

公开(公告)日：2003-10-16

申请号：PCT/US2003/010266

申请日：2003-04-03

Applicant: HONEYWELL INTERNATIONAL INC.

Inventor： LIU, Michael, S. ,  FECHNER, Paul, S. ,  REKSTAD, Jane, Kathleen ,  SINHA, Shankar, P.

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78651

Abstract: An SOI GAA device is created by etching a buried oxide layer of an SOI wafer structure that is provided over a silicon substrate. A portion of the buried oxide layer remains over the silicon substrate after etching. A plurality of silicon fingers is formed so that the silicon fingers extend over the remaining buried oxide layer. A gate oxide is formed all around each of the silicon fingers, and a common silicon gate is formed all around all of the gate oxides. A common source and a common drain are formed by suitably doping opposite ends of the silicon fingers leaving a channel therebetween.

Abstract translation: 通过蚀刻设置在硅衬底上的SOI晶片结构的掩埋氧化物层来产生SOI GAA器件。 在蚀刻之后，一部分掩埋氧化物层保留在硅衬底上。 形成多个硅指以使得硅指延伸超过剩余的掩埋氧化物层。 在每个硅指的周围形成栅极氧化物，并且在所有栅极氧化物周围形成共同的硅栅极。 共同的源极和公共漏极通过适当地掺杂硅指的相对端而在其间留下通道而形成。

公开(公告)号：WO2002073667A3

公开(公告)日：2002-09-19

申请号：PCT/US2002/007311

申请日：2002-03-12

Applicant: HONEYWELL INTERNATIONAL INC.

Inventor： FECHNER, Paul, S. ,  YUE, Cheisan

IPC: H01L21/74

Abstract: A method of forming a frontside contact to a Silicon-On-Insulator (SOI) wafer is described. A connection polysilicon (114) connects a silicon substrate layer (102) to a contact plug (118). This connection provides a means to ground or bias the bottom substrate of the SOI wafer. Spacers (122) may be added to provide additional doping.