公开(公告)号：WO2005031816A1

公开(公告)日：2005-04-07

申请号：PCT/SG2004/000268

申请日：2004-08-31

Applicant: INFINEON TECHNOLOGIES AG ,  ZHUANG, Haoren ,  EGGER, Ulrich ,  BRUCHHAUS, Rainer ,  HORNIK, Karl ,  LIAN, Jingyu ,  GERNHARDT, Stefan

Inventor： ZHUANG, Haoren ,  EGGER, Ulrich ,  BRUCHHAUS, Rainer ,  HORNIK, Karl ,  LIAN, Jingyu ,  GERNHARDT, Stefan

IPC: H01L21/02

CPC classification number: H01L27/11502 ,  H01L21/31122 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

Abstract: Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer (33) is deposited over an insulator (31). In a first etching stage, the ferroelectric material is etched to form openings (35) in it, leaving the insulating layer substantially intact. Then a conductive layer (39) is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the AI 2 O 3 layer (31), for making connections to conductive elements (3) beneath it. Thus, by the time the second etching step is performed, there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.

Abstract translation: 具有垂直结构的铁电体通过在绝缘体（31）上沉积铁电层（33）的工艺形成。 在第一蚀刻阶段，蚀刻铁电材料以在其中形成开口（35），使绝缘层基本上保持完整。 然后，将导电层（39）沉积到形成在铁电层中的开口中，在开口的侧面形成电极。 执行进一步蚀刻以在Al 2 O 3层（31）中形成间隙，以便连接到其下的导电元件（3）。 因此，在执行第二蚀刻步骤之前，已经有电极覆盖在铁电材料的侧面，而两者之间没有绝缘栅栏。

公开(公告)号：WO2005015614A1

公开(公告)日：2005-02-17

申请号：PCT/SG2004/000201

申请日：2004-07-06

Applicant: INFINEON TECHNOLOGIES AG ,  KABUSHIKI KAISHA TOSHIBA ,  ZHUANG, Haoren ,  EGGER, Ulrich ,  LIAN, Jingyu ,  GERNHARDT, Stefan ,  KANAYA, Hiroyuki

Inventor： ZHUANG, Haoren ,  EGGER, Ulrich ,  LIAN, Jingyu ,  GERNHARDT, Stefan ,  KANAYA, Hiroyuki

IPC: H01L21/02

CPC classification number: H01L28/86 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

Abstract: A ferroelectric device includes a bottom electrode (119) on which are formed ferrocapacitor elements (103) and, over the ferroelectric elements, top electrodes (101). The bottom electrodes are connected to lower layers of the device via conductive plugs (113), and the plugs and bottom electrodes are spaced apart by barrier elements (107) (109) of Ir and/or IrO 2 . The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO 2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.

Abstract translation: 铁电体器件包括底电极（119），在其上形成有铁电体元件（103），并且在铁电元件上方形成上电极（101）。 底部电极经由导电插塞（113）连接到器件的下层，并且插头和底部电极由Ir和/或IrO 2的阻挡元件（107）（109）间隔开。 阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。 这意味着在底电极的蚀刻期间不形成Ir栅栏。 另外，少量Ir和/或IrO 2通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料。

公开(公告)号：WO2005036612A2

公开(公告)日：2005-04-21

申请号：PCT/JP2004/014287

申请日：2004-09-22

Applicant: KABUSHIKI KAISHA TOSHIBA ,  Infineon Technologies AG ,  YAMAKAWA, Koji ,  NATORI, Katsuaki ,  YAMAZAKI, Soichi ,  ARISUMI, Osamu ,  ITOKAWA, Hiroshi ,  KANAYA, Hiroyuki ,  TOMIOKA, Kazuhiro ,  NAKAZAWA, Keisuke ,  TANIGUCHI, Yasuyuki ,  EGGER, Ulrich

Inventor： YAMAKAWA, Koji ,  NATORI, Katsuaki ,  YAMAZAKI, Soichi ,  ARISUMI, Osamu ,  ITOKAWA, Hiroshi ,  KANAYA, Hiroyuki ,  TOMIOKA, Kazuhiro ,  NAKAZAWA, Keisuke ,  TANIGUCHI, Yasuyuki ,  EGGER, Ulrich

IPC: H01L21/00

CPC classification number: H01L21/31144 ,  H01L21/32136 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: The present invention provides a method for manufacturing a semiconductor device equipped with a capacitor in which a dielectric film is used, wherein a complex oxide is used as a mask material when the dielectric film is etched.

Abstract translation: 本发明提供了一种制造半导体器件的方法，所述半导体器件配备有使用电介质膜的电容器，其中当蚀刻所述电介质膜时，使用复合氧化物作为掩模材料。

公开(公告)号：WO2005031856A1

公开(公告)日：2005-04-07

申请号：PCT/SG2004/000272

申请日：2004-08-31

Applicant: INFINEON TECHNOLOGIES AG ,  GERNHARDT, Stefan ,  ZHUANG, Haoren ,  EGGER, Ulrich

Inventor： GERNHARDT, Stefan ,  ZHUANG, Haoren ,  EGGER, Ulrich

IPC: H01L21/768

CPC classification number: H01L28/60

Abstract: A device and method for fabricating a device comprises forming a substrate and forming a contact plug through the substrate. A first electrode is formed on the substrate and a dielectric layer is formed on the first electrode. A second electrode is formed on the ferroelectric layer and an interlayer dielectric layer is applied to the second electrode and exposed surfaces of the first electrode and the ferroelectric layer. The interlayer dielectric layer is subjected to a chemical mechanical polishing process to expose a surface of the second electrode and a metal layer is deposited onto the polished interlayer dielectric layer and the exposed surface of the second electrode. The metal layer is then etched to provide an interconnection pattern to the second electrode.

Abstract translation: 用于制造器件的器件和方法包括形成衬底并通过衬底形成接触插塞。 在基板上形成第一电极，在第一电极上形成电介质层。 在铁电体层上形成第二电极，在第二电极和第一电极和铁电层的露出面上施加层间电介质层。 对层间介电层进行化学机械抛光工艺以暴露第二电极的表面，并且将金属层沉积到抛光的层间介电层和第二电极的暴露表面上。 然后蚀刻金属层以提供到第二电极的互连图案。

公开(公告)号：WO2004093169A1

公开(公告)日：2004-10-28

申请号：PCT/SG2004/000074

申请日：2004-03-30

Applicant: INFINEON TECHNOLOGIES AG ,  KABUSHIKI KAISHA TOSHIBA ,  ZHUANG, Haoren ,  EGGER, Ulrich ,  TOMIOKA, Kazuhiro

Inventor： ZHUANG, Haoren ,  EGGER, Ulrich ,  TOMIOKA, Kazuhiro

IPC: H01L21/02

CPC classification number: H01L28/55 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/60

Abstract: A process for the fabrication of a ferrocapacitor comprising depositing a first mask element 7 over a structure having a bottom electrode 1, a ferroelectric layer 3 and a top electrode 5. RIE etching is performed to remove portions of the top electrode 5 and the ferroelectric layer 3. Then a second hard mask element 9 is deposited over the first hardmask element. The second hard mask element is rounded by an etch back process, and its taper angle is controlled to be in the range 75-87°. A second RIE etching process is performed to remove portions of the bottom electrode 1. Due to the rounding of the second hard mask elements 9 low residues are formed on the sides of the etched bottom electrode 1.

Abstract translation: 一种用于制造铁电体的方法，包括在具有底部电极1，铁电体层3和顶部电极5的结构上沉积第一掩模元件7.进行RIE蚀刻以去除顶部电极5和铁电层的部分 然后，第二硬掩模元件9沉积在第一硬掩模元件上。 第二个硬掩模元件通过回蚀工艺圆化，其锥角控制在75-87°的范围内。 执行第二RIE蚀刻工艺以去除底部电极1的部分。由于第二硬掩模元件9的四舍五入，在蚀刻的底部电极1的侧面上形成低残留物。

公开(公告)号：WO2004068539A2

公开(公告)日：2004-08-12

申请号：PCT/SG2004/000018

申请日：2004-01-19

Applicant: INFINEON TECHNOLOGIES AG ,  KABUSHIKI KAISHA TOSHIBA ,  ZHUANG, Haoren ,  EGGER, Ulrich ,  TOMIOKA, Kazuhiro ,  LIAN, Jingyu ,  NAGEL, Nicolas ,  HILLIGER, Andreas ,  BEITEL, Gerhard

Inventor： ZHUANG, Haoren ,  EGGER, Ulrich ,  TOMIOKA, Kazuhiro ,  LIAN, Jingyu ,  NAGEL, Nicolas ,  HILLIGER, Andreas ,  BEITEL, Gerhard

IPC: H01L

CPC classification number: H01L28/55 ,  H01L21/31116 ,  H01L28/57

Abstract: The present invention provides a sidewall oxygen diffusion barrier and method for fabricating the sidewall oxygen diffusion barrier to reduce the diffusion of oxygen to contact plugs during CW hole reactive ion etch processing of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence, while in another embodiment the sidewall barrier is formed by etching back an oxygen barrier.

Abstract translation: 本发明提供一种侧壁氧扩散阻挡层和用于制造侧壁氧扩散阻挡层的方法，以在FeRAM器件的铁电电容器的CW孔反应离子蚀刻处理期间减少氧气对接触插塞的扩散。 在一个实施例中，侧壁屏障由衬底栅栏形成，而在另一个实施例中，侧壁屏障是通过蚀刻回氧屏障形成的。

公开(公告)号：WO2004051711A2

公开(公告)日：2004-06-17

申请号：PCT/SG2003/000271

申请日：2003-11-17

Applicant: INFINEON TECHNOLOGIES AG ,  EGGER, Ulrich ,  ZHUANG, Haoren ,  HORNIK, Karl

Inventor： EGGER, Ulrich ,  ZHUANG, Haoren ,  HORNIK, Karl

IPC: H01L21/00

CPC classification number: H01L28/55 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/31116 ,  H01L21/3162

Abstract: A method of forming a capacitor, comprises the steps of (a) forming a matrix of ferroelectric capacitor elements on a substrate, (b) forming a CAP layer over the ferroelectric capacitor elements, and (c) etching the CAP layer to a more uniform thickness. Also, a capacitor comprises a substrate layer, a matrix of ferroelectric capacitor elements including a first electrode layer substantially fixed relative to the substrate, a second electrode layer, and a ferroelectric layer sandwiched between the first and second electrode layers; a shoulder layer extending from the substrate to the matrix; and a CAP layer etched to have substantially constant thickness covering sides of the matrix extending beyond the substrate.

Abstract translation: 一种形成电容器的方法包括以下步骤：（a）在衬底上形成铁电电容器元件的矩阵，（b）在铁电电容器元件上形成CAP层，以及（c）将CAP层蚀刻成更均匀 厚度。 此外，电容器包括基板层，包括相对于基板基本上固定的第一电极层的铁电电容器元件的矩阵，第二电极层和夹在第一和第二电极层之间的铁电层; 从基底延伸到基体的肩层; 并且CAP层被蚀刻以具有基本上恒定的厚度，覆盖延伸超过衬底的矩阵的侧面。

公开(公告)号：WO2004030069A2

公开(公告)日：2004-04-08

申请号：PCT/SG2003/000220

申请日：2003-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAN, Jenny ,  ZHUANG, Haoren ,  EGGER, Ulrich ,  HORNIK, Karl

IPC: H01L21/311

CPC classification number: H01L28/55 ,  H01L21/31122

Abstract: A method of forming a ferroelectric capacitor, in particular for use in a FeRAM or high-k DRAM application, and a capacitor made by the method. The method comprises forming a first layer which is patterned, for example by a reactive ion etching method. A ferroelectric material is then formed over the patterned first layer. The morphology of the ferroelectric material will be dependent upon the patterning of the first layer. The ferroelectric layer is then patterned, for example using a wet etching or a reactive ion etching method. The etching will depend upon the morphology of the ferroelectric layer. After etching the ferroelectric layer, a conductive layer is provided over the ferroelectric layer to form a first electrode of the capacitor. If the first layer is a conductive layer, this forms the second electrode. If the first layer is a non-conductive layer,. the conductive layer is patterned to form both the first and second electrodes.

Abstract translation: 一种形成铁电电容器的方法，特别是用于FeRAM或高k DRAM应用中的方法以及由该方法制造的电容器。 该方法包括形成例如通过反应离子蚀刻方法图案化的第一层。 然后在图案化的第一层上形成铁电材料。 铁电材料的形态将取决于第一层的图案化。 然后，例如使用湿法蚀刻或反应离子蚀刻方法将铁电层图案化。 蚀刻将取决于铁电层的形态。 在腐蚀铁电层之后，在铁电层上提供导电层以形成电容器的第一电极。 如果第一层是导电层，则这形成第二电极。 如果第一层是非导电层， 图案化导电层以形成第一和第二电极。

公开(公告)号：WO2005031817A1

公开(公告)日：2005-04-07

申请号：PCT/SG2004/000269

申请日：2004-08-31

Applicant: INFINEON TECHNOLOGIES AG ,  ZHUANG, Haoren ,  BRUCHHAUS, Rainer ,  EGGER, Ulrich ,  LIAN, Jingyu ,  NAGEL, Nicolas

Inventor： ZHUANG, Haoren ,  BRUCHHAUS, Rainer ,  EGGER, Ulrich ,  LIAN, Jingyu ,  NAGEL, Nicolas

IPC: H01L21/02

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: A vertical capacitor of an FeRAM device is formed by depositing conductive material and etching it to form electrodes, which are located over openings in an insulating layer so that they are electrically connected to lower levels of the structure. A layer of ferroelectric material is formed on the sides of the electrodes, and etched to a desired, uniform thickness. Conductive material is deposited over the ferroelectric material to form a uniform surface onto which another insulating layer can be deposited. Since this process does not include etching of an insulating layer at a time between the formation of the electrodes and the deposition of the ferroelectric material, no fences of insulating material are formed between them. The geometry can be accurately controlled, to give uniform electric fields and reliable operating parameters.

Abstract translation: FeRAM器件的垂直电容器通过沉积导电材料并蚀刻形成电极，该电极位于绝缘层中的开口上方，使得它们电连接到结构的较低层。 在电极的侧面形成铁电材料层，并且蚀刻到期望的均匀厚度。 导电材料沉积在铁电材料上以形成可沉积另一绝缘层的均匀表面。 由于该方法不包括在形成电极之间的时间刻蚀绝缘层和铁电体的沉积，所以在它们之间不形成绝缘材料栅栏。 几何形状可以精确控制，给出均匀的电场和可靠的工作参数。

公开(公告)号：WO2005031814A1

公开(公告)日：2005-04-07

申请号：PCT/SG2004/000266

申请日：2004-08-31

Applicant: INFINEON TECHNOLOGIES AG ,  LIAN, Jingyu ,  EGGER, Ulrich ,  ZHUANG, Haoren

Inventor： LIAN, Jingyu ,  EGGER, Ulrich ,  ZHUANG, Haoren

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/75

Abstract: A method for fabricating a device and a device, such as a ferroelectric capacitor, having a substrate, a contact plug through the substrate, a first barrier layer on the substrate, a first electrode on the first barrier layer, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, comprises etching the second electrode and the dielectric layer of the device using a first hardmask, to shape the second electrode and the dielectric layer. The first hardmask is then removed and one or more encapsulating layers are applied to the second electrode and the dielectric layer. A further hardmask is applied to the one or more encapsulating layers. The first electrode is then etched according to the second hardmask down to the first barrier layer and the second hardmask is then removed from the one or more encapsulating layers.

Abstract translation: 一种制造器件和器件的方法，例如铁电电容器，具有衬底，通过衬底的接触插塞，衬底上的第一阻挡层，第一阻挡层上的第一电极，第一阻挡层上的电介质层 电极和第二电极，包括使用第一硬掩模蚀刻该器件的第二电极和介电层，以使第二电极和电介质层成型。 然后去除第一硬掩模，并且将一个或多个封装层施加到第二电极和电介质层。 另外的硬掩模应用于一个或多个封装层。 然后根据第二硬掩模将第一电极蚀刻到第一阻挡层，然后从一个或多个封装层移除第二硬掩模。