公开(公告)号：WO2013090297A1

公开(公告)日：2013-06-20

申请号：PCT/US2012/069018

申请日：2012-12-11

Applicant: INTEL CORPORATION

Inventor： LIU, Yen-Cheng ,  BLANKENSHIP, Robert G. ,  SANTHANAKRISHNAN, Geeyarpuram N. ,  SRINIVASA, Ganapati N. ,  CRETA, Kenneth C. ,  MUTHRASANALLUR, Sridhar ,  FAHIM, Bahaa

IPC: G06F9/46 ,  G06F12/08 ,  G06F9/06

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/452 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an ntegrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器和耦合到多核处理器的至少一个IO设备之间进行接口的整合输入/输出（IIO）模块，以及 高速缓存代理，用于对多个核心和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。

公开(公告)号：WO2015099730A1

公开(公告)日：2015-07-02

申请号：PCT/US2013/077785

申请日：2013-12-26

Applicant: INTEL CORPORATION ,  DAS SHARMA, Debendra ,  BLANKENSHIP, Robert G. ,  CHITTOR, Suresh S. ,  CRETA, Kenneth C. ,  FLEISCHER, Balint ,  JEN, Michelle C. ,  KUMAR, Mohan J. ,  MORRIS, Brian S.

Inventor： DAS SHARMA, Debendra ,  BLANKENSHIP, Robert G. ,  CHITTOR, Suresh S. ,  CRETA, Kenneth C. ,  FLEISCHER, Balint ,  JEN, Michelle C. ,  KUMAR, Mohan J. ,  MORRIS, Brian S.

IPC: G06F13/14 ,  G06F13/20 ,  G06F12/00

CPC classification number: G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Abstract translation: 共享存储器控制器是通过数据链路从多个独立节点服务加载和存储从数据链路接收的操作，以提供对共享存储器资源的访问。 要允许多个独立节点中的每一个访问共享存储器资源的相应部分。 在数据链路上发送互连协议数据和存储器访问协议数据，并且可以定义和识别互连协议数据和存储器访问协议数据之间的转换。

公开(公告)号：WO2013103339A1

公开(公告)日：2013-07-11

申请号：PCT/US2012/020175

申请日：2012-01-04

Applicant: INTEL CORPORATION ,  CRETA, Kenneth C. ,  HORIHAN, Jason W. ,  BLANKENSHIP, Robert G. ,  CHENG, Kai

Inventor： CRETA, Kenneth C. ,  HORIHAN, Jason W. ,  BLANKENSHIP, Robert G. ,  CHENG, Kai

IPC: G06F13/14 ,  G06F12/00 ,  G06F15/80

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/16 ,  G06F13/4234 ,  G06F2206/1014 ,  G11C13/0002 ,  G11C14/009

Abstract: Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了在相干链路和存储器扩展之间提供双模功能相关的方法和装置。 在一个实施例中，处理器经由相干互连耦合到一个或多个代理。 处理器还通过链路逻辑耦合到一个或多个双列直插内存模块（DIMM）。 该逻辑支持基于单个数据位读取或写入指向一个或多个DIMM的命令。 还公开并要求保护其他实施例。