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    PERFORMING DYNAMIC POWER CONTROL OF PLATFORM DEVICES
    3.
    发明申请
    PERFORMING DYNAMIC POWER CONTROL OF PLATFORM DEVICES 审中-公开
    执行平台设备的动态功率控制

    公开(公告)号：WO2016133664A1

    公开(公告)日：2016-08-25

    申请号：PCT/US2016/015075

    申请日：2016-01-27

    Applicant: INTEL CORPORATION

    Inventor： VARMA, Ankush ,  SISTLA, Krishnakanth V. ,  SRINIVASAN, Vasudevan ,  GORBATOV, Eugene ,  HENROID, Andrew D. ,  COOPER, Barnes ,  BROWNING, David W. ,  THERIEN, Guy M. ,  SONGER, Neil W. ,  HERMERDING II, James G.

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/50 ,  Y02B70/126 ,  Y02D10/171

    Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括执行指令的至少一个核心和用于从多个设备接收功率能力信息的功率控制逻辑以耦合到处理器并且向设备分配平台功率预算，为 分配相应设备被供电的设备将第一功率电平传送到设备，并且动态地减少要分配给第一设备的第一功率并且增加要分配给第二设备的第二功率，以响应于 来自第二设备的更高功率电平的请求。 描述和要求保护其他实施例。

    METHOD AND SYSTEM FOR DETERMINING AN ENERGY-EFFICIENT OPERATING POINT OF A PLATFORM
    6.
    发明申请
    METHOD AND SYSTEM FOR DETERMINING AN ENERGY-EFFICIENT OPERATING POINT OF A PLATFORM 审中-公开
    用于确定平台能量有效操作点的方法和系统

    公开(公告)号：WO2013002864A1

    公开(公告)日：2013-01-03

    申请号：PCT/US2012/032525

    申请日：2012-04-06

    Applicant: INTEL CORPORATION ,  HENROID, Andrew D. ,  GORBATOV, Eugene ,  DIEFENBAUGH, Paul S.

    Inventor： HENROID, Andrew D. ,  GORBATOV, Eugene ,  DIEFENBAUGH, Paul S.

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of the processing cores and/or platform components in the platform to achieve maximum system energy efficiency. By using the characteristics of the workload and/or platform to determine the optimum settings of the platform, the logic of the platform facilitates performance guarantees of the platform while minimizing the energy consumption of the processor core and/or platform. The logic of the platform identifies opportunities to run the processing cores at higher performance levels which decreases the execution time of the workload and transitions the platform to a low-power system idle state after the completion of the execution of the workload. Since the execution time of the workload is reduced, the platform spends more time in the low-power system idle state and therefore the overall system energy consumption is reduced.

    Abstract translation: 一种用于确定平台或系统的节能工作点的方法和系统。 该平台具有动态管理平台中处理核心和/或平台组件的设置以实现最大系统能量效率的逻辑。 通过使用工作负载和/或平台的特征来确定平台的最佳设置，平台的逻辑有助于平台的性能保证，同时最小化处理器核心和/或平台的能量消耗。 该平台的逻辑确定了以更高的性能水平运行处理核心的机会，这降低了工作负载的执行时间，并且在完成工作负载完成后将平台转换为低功耗系统空闲状态。 由于工作负载的执行时间减少，平台在低功耗系统空闲状态下花费更多时间，因此整体系统能耗降低。

    APPARATUSES AND METHODS TO SPAWN MULTIPLE VIRTUAL SERIAL BUS HUB INSTANCES ON A SAME PHYSICAL SERIAL BUS HUB
    7.
    发明申请
    APPARATUSES AND METHODS TO SPAWN MULTIPLE VIRTUAL SERIAL BUS HUB INSTANCES ON A SAME PHYSICAL SERIAL BUS HUB 审中-公开

    公开(公告)号：WO2018093519A1

    公开(公告)日：2018-05-24

    申请号：PCT/US2017/057163

    申请日：2017-10-18

    Applicant: INTEL CORPORATION

    Inventor： LAWLESS, Sean ,  HENROID, Andrew D.

    IPC: G06F13/38

    CPC classification number: G06F13/4068 ,  G06F13/4282

    Abstract: Methods and apparatuses relating to circuitry to spawn multiple virtual serial bus hub instances on a same physical serial bus hub are described. In one embodiment, an apparatus includes a serial bus hub to electrically couple a plurality of hosts and a plurality of devices, and a circuit to spawn a first virtual hub instance that is bound to a first host of the plurality of hosts and a first device of the plurality of devices, and spawn a concurrently usable, second virtual hub instance that is bound to a second host of the plurality of hosts and a second device of the plurality of devices.

    THREAD MIGRATION SUPPORT FOR ARCHITECTUALLY DIFFERENT CORES
    9.
    发明申请
    THREAD MIGRATION SUPPORT FOR ARCHITECTUALLY DIFFERENT CORES 审中-公开
    用于建筑物不同角度的螺纹移动支撑

    公开(公告)号：WO2014105010A1

    公开(公告)日：2014-07-03

    申请号：PCT/US2012/071686

    申请日：2012-12-26

    Applicant: INTEL CORPORATION

    Inventor： NAIK, Mishali ,  SRINIVASA, Ganapati N. ,  NAVEH, Alon ,  SODHI, Inder M. ,  NARVAEZ, Paolo ,  GORBATOV, Eugene ,  WEISSMANN, Eliezer ,  HENROID, Andrew D. ,  HERDRICH, Andrew J. ,  KHANNA, Gaurav ,  HAHN, Scott D. ,  BRETT, Paul ,  KOUFATY, David A. ,  SUBBAREDDY, Dheeraj R. ,  PRABHAKARAN, Abirami

    IPC: G06F15/80 ,  G06F1/26 ,  G06F13/14 ,  G06F9/06

    CPC classification number: G06F9/461 ,  G06F9/3851 ,  G06F9/4856 ,  G06F9/5094 ,  Y02D10/22

    Abstract: According to one embodiment, a processor includes a plurality of processor cores for executing a plurality of threads, a shared storage communicatively coupled to the plurality of processor cores, a power control unit (PCU) communicatively coupled to the plurality of processors to determine, without any software (SW) intervention, if a thread being performed by a first processor core should be migrated to a second processor core, and a migration unit, in response to receiving an instruction from the PCU to migrate the thread, to store at least a portion of architectural state of the first processor core in the shared storage and to migrate the thread to the second processor core, without any SW intervention, such that the second processor core can continue executing the thread based on the architectural state from the shared storage without knowledge of the SW.

    Abstract translation: 根据一个实施例，处理器包括用于执行多个线程的多个处理器核心，通信地耦合到所述多个处理器核心的共享存储器，通信地耦合到所述多个处理器的功率控制单元（PCU），以便在没有 如果由第一处理器核心执行的线程应该迁移到第二处理器核心的任何软件（SW）干预，以及迁移单元，响应于接收到来自PCU的指令来迁移线程，以存储至少一个 共享存储器中的第一处理器核心的架构状态的一部分，并且将线程迁移到第二处理器核心，而没有任何SW干预，使得第二处理器核心可以基于来自共享存储器的架构状态继续执行线程，而没有 SW的知识。

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