公开(公告)号：WO2022098342A1

公开(公告)日：2022-05-12

申请号：PCT/US2020/058622

申请日：2020-11-03

Applicant: INTEL CORPORATION

Inventor： THAKUR, Jayprakash ,  DEGANI, Ofir ,  KRONFELD, Ronen ,  RESHEF, Ehud ,  SUH, Seong-Youp, J. ,  SHOSHANA, Tal ,  MANN, Eytan ,  TAMRAKAR, Maruti ,  RAVI, Ashoke ,  CAMACHO PEREZ, Jose Rodrigo ,  HUUSARI, Timo Sakari ,  BOROKHOVICH, Eli ,  RUBIN, Amir ,  BENJAMIN, Ofer ,  YANG, Tae Young ,  SKINNER, Harry ,  LEE, Kwan Ho ,  LEE, Jaejin ,  HAN, Dong-Ho ,  GROSS, Shahar ,  SEGEV, Eran ,  KAMGAING, Telesphor

IPC: H04B1/50 ,  H04B1/00 ,  H04B1/44 ,  H01Q1/24

Abstract: In various aspects, a radio frequency circuit is provided. The radio frequency circuit may include a substrate that may include a radio frequency front-end to antenna (RF FE-to-Ant) connector. The RF FE-to-Ant connector may include a conductor track structure and a substrate connection structure coupled to the conductor track structure. The substrate may include radio frequency front-end circuitry monolithically integrated in the substrate. The substrate connection structure may include at least one of a solderable structure, a weldable structure, or an adherable structure. The substrate connection structure may be configured to form at least one radio frequency signal interface with an antenna circuit connection structure of a substrate-external antenna circuit. The substrate may include an edge region. The substrate connection structure may be disposed in the edge region.

公开(公告)号：WO2022066255A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/039169

申请日：2021-06-25

Applicant: INTEL CORPORATION

Inventor： BENJAMIN, Ofer ,  BOROKHOVICH, Eli ,  CARLTON, Brent ,  DEGANI, Ofir ,  KRONFELD, Ronen ,  PELLERANO, Stefano ,  RAHMAN, Mustafijur ,  RESHEF, Ehud ,  ZUR, Sarit

IPC: H04B1/10 ,  H04B1/06 ,  G06F7/00 ,  H04B1/12 ,  H04B1/02

Abstract: A transceiver may include a transmit path and a receive path that are each coupled to a radio frequency (RF) interface, and a self-interference canceller (SIC). The SIC is coupled between the transmit and the receive paths. The SIC is configured to cancel a self-interference signal from a received signal on the receive path based on a transmit signal on the transmit path.

公开(公告)号：WO2021133398A1

公开(公告)日：2021-07-01

申请号：PCT/US2019/068638

申请日：2019-12-27

Applicant: INTEL CORPORATION

Inventor： RAVI, Ashoke ,  KRONFELD, Ronen ,  DEGANI, Ofir

IPC: H03L7/24 ,  H03L7/083 ,  H03L7/099 ,  H03L7/18

Abstract: A radio-frequency integrated circuit (RFIC) configured to generate a synthesized clock includes a phase locked loop (PLL) configured to divide down a clock to a non-harmonic frequency; a plurality of multi-phase injection locked clock multipliers (ILCM) directly connected to a plurality of transceiver chains; wherein the PLL is further configured to distribute a divided down clock to at least one of the plurality of multi-phase ILCMs; wherein the plurality of multiphase ILCMs are configured to select a phase of and multiply the divided down clock to synthesize a desired harmonic frequency of the clock and suppress an undesired harmonic frequency of the clock.