公开(公告)号：WO2017039916A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/045135

申请日：2016-08-02

Applicant: INTEL CORPORATION

Inventor： TRIKA, Sanjeev N. ,  GRIMSRUD, Knut S. ,  WYSOCKI, Piotr

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685 ,  G06F11/2015 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0888 ,  G06F2201/805 ,  G06F2212/7203

Abstract: Technologies for establishing and managing a high-performance memory region of a solid state drive include reserving a region of a volatile memory of the solid state drive for storage of host data. Memory accesses received from a host may be directed toward the reserved region of the volatile memory or toward a non-volatile memory of the solid state drive. Due to the structure of the volatile memory, memory accesses to the reserved region may exhibit lower access timing relative to memory accesses to the non-volatile memory. As such, the reserved region may be utilized as storage space for journaling and logging of data and/or other applications. Upon shutdown or a power failure event, data stored in the reserved region of the volatile memory is copied to the non-volatile memory and subsequently reinstated to the volatile memory upon the next initialization event.

Abstract translation: 用于建立和管理固态驱动器的高性能存储器区域的技术包括保留用于存储主机数据的固态驱动器的易失性存储器的区域。 从主机接收到的存储器访问可以指向易失性存储器的保留区域或朝向固态驱动器的非易失性存储器。 由于易失性存储器的结构，相对于对非易失性存储器的存储器访问，对保留区域的存储器访问可以呈现较低的访问时序。 因此，保留区域可以用作用于日志记录和记录数据和/或其他应用的存储空间。 在关闭或电源故障事件时，存储在易失性存储器的保留区域中的数据被复制到非易失性存储器中，并且随后在下一个初始化事件时恢复到易失性存储器。

公开(公告)号：WO2022271042A1

公开(公告)日：2022-12-29

申请号：PCT/PL2021/050045

申请日：2021-06-25

Applicant: INTEL CORPORATION ,  GUIM BERNAT, Francesc ,  DOSHI, Kshitij Arun ,  WEBER, Karol ,  PIOTROWSKI, Marek ,  WYSOCKI, Piotr

Inventor： GUIM BERNAT, Francesc ,  DOSHI, Kshitij Arun ,  WEBER, Karol ,  PIOTROWSKI, Marek ,  WYSOCKI, Piotr

IPC: G06F9/50 ,  H04L41/5019 ,  G06F2209/501 ,  G06F2209/506 ,  G06F9/5027 ,  G06F9/5072 ,  G06F9/5077 ,  H04L41/0823 ,  H04L41/0897

Abstract: A computing node includes a NIC and processing circuitry configured to select a subset of computing resources from a set of available computing resources to initiate a parameter sweep associated with a parameter sweep request received. A plurality of settings is applied to each computing resource of the subset to generate a plurality of resource mappings during the parameter sweep. Each resource mapping of the plurality of resource mappings indicates at least one computing resource of the subset and a corresponding at least one setting of the plurality of settings. Telemetry information for the subset of computing resources is retrieved, the telemetry information is generated during the parameter sweep. A resource mapping of the plurality of resource mappings is selected based on a comparison of the telemetry information with an SLO. A reconfiguration of the available computing resources is performed based on the selected resource mapping.

公开(公告)号：WO2021163973A1

公开(公告)日：2021-08-26

申请号：PCT/CN2020/076072

申请日：2020-02-20

Applicant: INTEL CORPORATION ,  TRIKA, Sanjeev ,  TUCKER, Gregory ,  HARRIS, James ,  HUGHES, Jonathan ,  WYSOCKI, Piotr ,  CAO, Gang ,  DAI, Qihua ,  WALKER, Benjamin ,  YANG, Ziye ,  LIU, Xiaodong ,  LIU, Changpeng ,  ELLIS, Jackson

Inventor： TRIKA, Sanjeev ,  TUCKER, Gregory ,  HARRIS, James ,  HUGHES, Jonathan ,  WYSOCKI, Piotr ,  CAO, Gang ,  DAI, Qihua ,  WALKER, Benjamin ,  YANG, Ziye ,  LIU, Xiaodong ,  LIU, Changpeng ,  ELLIS, Jackson

IPC: G11C7/10

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.

公开(公告)号：WO2018063484A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/044016

申请日：2017-07-26

Applicant: INTEL CORPORATION

Inventor： KAMINSKI, Maciej ,  WYSOCKI, Piotr ,  PTAK, Slawomir

IPC: G06F12/0802 ,  G06F13/16

CPC classification number: G06F12/0873 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/068 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/221 ,  G06F2212/2228 ,  G06F2212/224 ,  G06F2212/271 ,  G06F2212/284 ,  G06F2212/3042 ,  G06F2212/305 ,  G06F2212/313

Abstract: An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region system memory.

Abstract translation: 描述了一种装置。 该设备包括存储器控制器，该存储器控制器包括逻辑电路以在系统存储器的非易失性区域中实现大容量存储高速缓存。 系统内存的非易失性区域用于支持直接从非易失性区域系统内存中执行程序代码。