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    SUSPENDED INDUCTOR MICROELECTRONIC STRUCTURES
    4.
    发明申请
    SUSPENDED INDUCTOR MICROELECTRONIC STRUCTURES 审中-公开
    悬挂电感器微电子结构

    公开(公告)号：WO2013162519A1

    公开(公告)日：2013-10-31

    申请号：PCT/US2012/034798

    申请日：2012-04-24

    Applicant: INTEL CORPORATION ,  MANUSHAROW, Mathew, J. ,  ROY, Mihir ,  RADHAKRISHNAN, Kaladhar ,  MALLIK, Debendra ,  BURTON, Edward

    Inventor： MANUSHAROW, Mathew, J. ,  ROY, Mihir ,  RADHAKRISHNAN, Kaladhar ,  MALLIK, Debendra ,  BURTON, Edward

    IPC: H01L23/12 ,  H01L23/48

    CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19106 ,  H05K1/111 ,  H05K1/141 ,  H05K2201/1003

    Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

    Abstract translation: 本说明书涉及制造微电子结构的领域。 微电子结构可以包括具有开口的微电子衬底，其中开口可以通过微电子衬底形成，或者可以是在微电子衬底中形成的凹部。 微电子封装可以附接到微电子衬底，其中微电子封装可以包括具有第一表面和相对的第二表面的插入件。 微电子器件可以附接到插入器第一表面，并且插入器可以通过插入器第一表面附接到微电子衬底，使得微电子器件延伸到开口中。 至少一个次级微电子器件可以附接到插入件第二表面。

    BACKSIDE RECESS IN MOTHERBOARD WITH THERMALLY CONDUCTIVE MOLD
    7.
    发明申请
    BACKSIDE RECESS IN MOTHERBOARD WITH THERMALLY CONDUCTIVE MOLD 审中-公开

    公开(公告)号：WO2022056732A1

    公开(公告)日：2022-03-24

    申请号：PCT/CN2020/115606

    申请日：2020-09-16

    Applicant: INTEL CORPORATION ,  RADHAKRISHNAN, Kaladhar ,  SHEN, Wei

    Inventor： RADHAKRISHNAN, Kaladhar ,  SHEN, Wei

    IPC: H01L23/48 ,  H01L21/768

    Abstract: Embodiments disclosed herein include microelectronic boards and electronic systems. In an embodiment, a microelectronic board comprises aboard substrate, where the board substrate has a first thickness between a first surface and a second surface opposite from the first surface. In an embodiment, a recess is formed into the first surface of the board substrate, where the recess comprises a third surface between the first surface and the second surface. In an embodiment, the board substrate has a second thickness between the third surface and the second surface. In an embodiment, the microelectronic board further comprises a voltage regulator (VR) module attached to the third surface.

    ARRAY CAPACITORS WITH VOIDS TO ENABLE A FULL-GRID SOCKET
    8.
    发明申请
    ARRAY CAPACITORS WITH VOIDS TO ENABLE A FULL-GRID SOCKET 审中-公开
    阵列电容器可以使用全桥式插座

    公开(公告)号：WO2005067045A1

    公开(公告)日：2005-07-21

    申请号：PCT/US2004/043339

    申请日：2004-12-23

    Applicant: INTEL CORPORATION ,  RADHAKRISHNAN, Kaladhar ,  WOOD, Dustin, P. ,  HOLMBERG, Nicholas, L.

    Inventor： RADHAKRISHNAN, Kaladhar ,  WOOD, Dustin, P. ,  HOLMBERG, Nicholas, L.

    IPC: H01L23/64

    CPC classification number: H01G4/242 ,  H01G2/06 ,  H01L23/50 ,  H01L23/66 ,  H01L24/10 ,  H01L2224/16225 ,  H01L2924/14

    Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers (201, 203…) interleaved with a number of second conductive layers (202, 204…) and a number of dielectric layers (211-220) separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias (331, 333…) to electrically connect the first conductive layers and a number of second conductive vias (334, 336…) to electrically connect the second conductive layers. The array capacitor is provided with openings (155, 371, 372, 373) which are configured to enable pins (135) from an IC package (120) to pass through.

    Abstract translation: 描述了与安装在IC封装上的集成电路（IC）一起使用的阵列电容器。 阵列电容器包括与多个第二导电层（202,204 ...）交错的多个第一导电层（201,203 ...）和分隔相邻的导电层的多个电介质层（211-220）。 阵列电容器还包括多个第一导电通孔（331,333 ...），以电连接第一导电层和多个第二导电通孔（334,336 ...）以电连接第二导电层。 阵列电容器设置有开口（155,371,372,373），其被配置为使得来自IC封装（120）的引脚（135）能够通过。

    PLANAR MAGNETIC RADIAL INDUCTORS TO ENABLE VR DISAGGREGATION
    10.
    发明申请
    PLANAR MAGNETIC RADIAL INDUCTORS TO ENABLE VR DISAGGREGATION 审中-公开

    公开(公告)号：WO2022066334A1

    公开(公告)日：2022-03-31

    申请号：PCT/US2021/047175

    申请日：2021-08-23

    Applicant: INTEL CORPORATION

    Inventor： RADHAKRISHNAN, Kaladhar

    IPC: H01L23/522 ,  H05K1/16

    Abstract: Embodiments disclosed herein include electronic packages with embedded inductors. In an embodiment, an electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment, the electronic package further comprises an inductor embedded in the package substrate, where the inductor comprises: a trace with a first end and a second end. In an embodiment, a magnetic material surrounds the trace between the first end and the second end. In an embodiment, a first via is connected to the first end, and a second via is connected to the second end.

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