公开(公告)号：WO2013095339A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065905

申请日：2011-12-19

Applicant: INTEL CORPORATION ,  WATTS, Nicholas R. ,  WU, Tao

Inventor： WATTS, Nicholas R. ,  WU, Tao

IPC: H01L23/488

CPC classification number: H01L23/49816 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips.

Abstract translation: 一个插入器，用于在底部芯片周围形成框架，该框架结合到封装衬底上，并与顶部芯片或封装件对准，以使底部芯片间隙。 插入器具有排列在第一侧上的引脚，该引脚被排列到封装衬底上，用于降低插入件z-高度，并且排列在顶部封装（芯片）所接合的第二侧上的焊盘）。 在组装期间，插入器插针可以被压在预焊焊盘上，并且焊料回流以将插入件连接到封装衬底。 然后将顶部封装（芯片）连接到插入器的相对侧，以集成第一和第二芯片。

公开(公告)号：WO2012040724A1

公开(公告)日：2012-03-29

申请号：PCT/US2011/053307

申请日：2011-09-26

Applicant: INTEL CORPORATION ,  WU, Tao ,  WATTS, Nicholas R.

Inventor： WU, Tao ,  WATTS, Nicholas R.

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L21/486 ,  C23C18/1653 ,  H01L23/142 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Electronic assemblies including coreless substrates and their manufacture using electrolytic plating, are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.

Abstract translation: 描述了包括无芯基板的电子组件及其使用电解电镀的制造。 一种方法包括提供包括金属的芯，并在芯上形成电介质材料。 该方法还包括在电介质材料中形成通孔，定位为使金属区域露出的通孔。 该方法还执行金属的电解电镀到通孔和金属区域中，其中在将金属电解电镀到通孔中并将电流传送到金属区域时，芯与电源电耦合。 该方法还包括在金属电镀到通孔中之后去除金属芯。 描述和要求保护其他实施例。