公开(公告)号：WO2012106183A1

公开(公告)日：2012-08-09

申请号：PCT/US2012/022801

申请日：2012-01-26

Applicant: MEGICA CORPORATION ,  LIN, Mou-Shiung ,  YANG, Ping-Jung ,  LO, Hsin-Jung ,  LIU, Te-Sheng ,  LEE, Jin-Yuan

Inventor： LIN, Mou-Shiung ,  YANG, Ping-Jung ,  LO, Hsin-Jung ,  LIU, Te-Sheng ,  LEE, Jin-Yuan

IPC: H01L21/98 ,  H01L25/065 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L21/683 ,  H01L21/8234

CPC classification number: H01L25/0657 ,  H01L21/76229 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48755 ,  H01L2224/48799 ,  H01L2224/48824 ,  H01L2224/48855 ,  H01L2224/80896 ,  H01L2224/8385 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12036 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Multichip packages or multichip modules may include stacked chips and through silicon/substrate vias (TSVs) formed using enclosure-first technology. Enclosure-first technology may include forming an isolation enclosure associated with a TSV early in the fabrication process, without actually forming the associated TSV. The TSV associated with the isolation enclosure is formed later in the fabrication process. The enclosure-first technology allows the isolation enclosures to be used as alignment marks for stacking additional chips. The stacked chips can be connected to each other or to an external circuit such that data input is provided through the bottom-most (or topmost) chip, data is output from the bottom-most (or topmost) chip. The multichip package may provide a serial data connection, and a parallel connection, to each of the stacked chips.

Abstract translation: 多芯片封装或多芯片模块可以包括堆叠芯片和通过使用封装第一技术形成的硅/衬底通孔（TSV）。 外壳首先技术可以包括在制造过程的早期形成与TSV相关联的隔离外壳，而不实际形成相关的TSV。 与隔离罩相关联的TSV在制造过程中稍后形成。 封装第一技术允许隔离外壳用作堆叠附加芯片的对准标记。 堆叠的芯片可以彼此连接或连接到外部电路，使得通过最底部（或最上面）芯片提供数据输入，数据从最底部（或最顶端）的芯片输出。 多芯片封装可以向每个堆叠的芯片提供串行数据连接和并联连接。

公开(公告)号：WO2016209837A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/038568

申请日：2016-06-21

Applicant: INVENSAS CORPORATION

Inventor： GAMINI, Nader

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/36 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/186 ,  H05K2201/10378 ,  H05K2203/0235

Abstract: Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.

Abstract translation: 提供了具有嵌入式跟踪互连的层压插入器和封装。 通过在多个晶片或平板上沉积导电迹线，然后将这些衬底层压成堆叠，从而嵌入导电迹线，用于制造插入器或封装的示例性工艺在封装中实现垂直导电通孔。 将层叠的叠层切成中介层或电子封装的尺寸。 然后将切片堆叠的一侧用作插入器或封装的顶部，将一些水平放置的迹线变成垂直导电通孔。 可以通过在顶表面和底表面以及主动和被动元件上添加再分布层来完成或开发中介层或封装。 电子元件也可以嵌入叠层。 一些堆叠层可以是活动管芯，例如存储器控制器，存储器存储阵列和处理器，以形成存储器子系统或独立的计算设备。

公开(公告)号：WO2012011929A1

公开(公告)日：2012-01-26

申请号：PCT/US2010/052462

申请日：2010-10-13

Applicant: TESSERA, INC. ,  OGANESIAN, Vage ,  MOHAMMED, Llyas ,  MITCHELL, Craig ,  HABA, Belgacem ,  SAVALIA, Piyush

Inventor： OGANESIAN, Vage ,  MOHAMMED, Llyas ,  MITCHELL, Craig ,  HABA, Belgacem ,  SAVALIA, Piyush

IPC: H01L21/302 ,  B32B5/00

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L29/0657 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A structure including a first semiconductor chip 20 with front and rear surfaces 24, 26 and a cavity 36 in the rear surface. A second semiconductor chip 70 is mounted within the cavity. The first chip 20 may have vias 48 extending from the cavity to the front surface and via conductors 54 within these vias serving to connect the additional microelectronic element 70 to the active elements of the first chip 20. The structure may have a volume comparable to that of the first chip 20 alone and yet provide the functionality of a multi-chip assembly. A composite chip 720 incorporating a body 722 and a layer 702 of semiconductor material mounted on a front surface 724 of the body similarly may have a cavity 736 extending into the body from the rear surface 726 and may have an additional microelectronic element 770 mounted in such cavity 736.

Abstract translation: 包括在后表面中具有前表面24和后表面26的第一半导体芯片20和空腔36的结构。 第二半导体芯片70安装在腔内。 第一芯片20可以具有从空腔延伸到前表面的通孔48，以及用于将附加微电子元件70连接到第一芯片20的有源元件的这些通孔内的导体54。结构可具有与之相当的体积 的第一芯片20，并提供多芯片组件的功能。 装配有主体722的复合芯片720和安装在主体的前表面724上的半导体材料层类似地可以具有从后表面726延伸到主体中的空腔736，并且可以具有安装在其上的附加微电子元件770 空腔736。

公开(公告)号：WO2011109044A1

公开(公告)日：2011-09-09

申请号：PCT/US2010/052850

申请日：2010-10-15

Applicant: XILINX, INC.

Inventor： RAHMAN, Arifur ,  MURALI, Venkatesan

IPC: H01L21/98 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/68 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/2902 ,  H01L2224/29187 ,  H01L2224/30181 ,  H01L2224/30183 ,  H01L2224/32137 ,  H01L2224/73267 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/83005 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/145 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

Abstract: A composite integrated circuit (IC, 100) combines a first IC die (chip, 102) having a first on-chip interconnect structure (1 14) and a second IC die (104) having a second on-chip interconnect structure (1 15) on a reconstructed wafer base (108). The second IC die is edge-bonded to the first IC die with oxide-to- oxide edge bonding (1 10). A chip-to-chip interconnect structure (1 18) electrically couples the first IC die and the second IC die. Methods of fabricating such a composite IC are also described.

Abstract translation: 复合集成电路（IC，100）组合具有第一片上互连结构（114）的第一IC裸片（芯片102）和具有第二片上互连结构（115）的第二IC裸片（104） ）在重建的晶片基座（108）上。 第二IC裸片与氧化物 - 氧化物边缘接合（110）边缘接合到第一IC裸片。 芯片到芯片互连结构（118）电耦合第一IC管芯和第二IC管芯。 还描述了制造这种复合IC的方法。

公开(公告)号：WO2016081730A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/061592

申请日：2015-11-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YE, Seng, Kim ,  NG, Hong, Wan

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G06F13/1668 ,  G06F13/1694 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/04 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/13083 ,  H01L2224/1319 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81855 ,  H01L2224/81856 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83874 ,  H01L2224/92227 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/83101 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/83

Abstract: Memory devices with controllers under stacks of memory packages and associated systems and methods are disclosed herein. In one embodiment, a memory device is configured to couple to a host and can include a substrate, a stack of memory packages, and a controller positioned between the stack and the substrate. The controller can manage data stored by the memory packages based on commands from the host.

Abstract translation: 本文公开了具有位于堆栈内存控制器的相关系统和方法的存储器件。 在一个实施例中，存储器设备被配置为耦合到主机并且可以包括衬底，堆叠的存储器封装以及位于堆和衬底之间的控制器。 控制器可以根据来自主机的命令来管理内存包存储的数据。

公开(公告)号：WO2015168206A1

公开(公告)日：2015-11-05

申请号：PCT/US2015/028138

申请日：2015-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： NG, Hong Wan ,  YE, Seng Kim

IPC: H01L23/12

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

Abstract translation: 本文公开了具有支撑构件和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括封装衬底，附接到封装衬底的第一半导体管芯以及也附接到封装衬底的多个支撑构件。 多个支撑构件可以包括第一支撑构件和设置在第一半导体管芯的相对侧的第二支撑构件，并且第二半导体管芯可以联接到支撑构件，使得第二半导体管芯的至少一部分 在第一个半导体芯片上。

公开(公告)号：WO2014158388A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/015810

申请日：2014-02-11

Applicant: MARVELL WORLD TRADE LTD. ,  KAO, Huahung ,  LIOU, Shiann-Ming

Inventor： KAO, Huahung ,  LIOU, Shiann-Ming

IPC: H01L25/10 ,  H01L23/34 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure provide a package on package arrangement comprising a first package (804,904) including a substrate layer (116) including a top side (117a), and a bottom side (117b) that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface (117a), and a first die (118) coupled to the bottom side of the substrate layer. The arrangement also comprises a second package (802,902) including a plurality of rows of solder balls (806,906) and at least one of one or both of an active component or a passive component (810,910,920). The second package is attached, via the plurality of rows of solder balls, to the substantially flat surface of the top side of the substrate layer of the first package. The active component and/or a passive component (810,910,920) is attached to the substantially flat surface of the top side of the substrate layer of the first package.

Abstract translation: 本公开的实施例提供了一种包装装置，其包括第一包装（804,904），第一包装（804,904）包括包括顶侧（117a）的底层（116）和与顶侧相对的底侧（117b），其中 衬底层的顶侧限定了基本平坦的表面（117a），以及耦合到衬底层的底侧的第一管芯（118）。 该装置还包括包括多排焊球（806,906）和活动部件或无源部件（810,910,920）中的一个或两个中的至少一个的第二封装（802,902）。 第二包装通过多排焊球附接到第一包装的基底层的顶侧的基本上平坦的表面。 有源部件和/或无源部件（810,910,920）附接到第一封装的衬底层的顶侧的基本上平坦的表面。

公开(公告)号：WO2013028435A1

公开(公告)日：2013-02-28

申请号：PCT/US2012/050953

申请日：2012-08-15

Applicant: Marvell World Trade Ltd. ,  KAO, Huahung ,  LIOU, Shiann-Ming

Inventor： KAO, Huahung ,  LIOU, Shiann-Ming

IPC: H01L25/10

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Abstract translation: 本公开的实施例提供了一种包装装置，包括底部包装和第二包装。 第一包装包括基底层，其包括（i）顶侧和（ii）与顶侧相对的底侧。 此外，顶侧限定基本平坦的表面。 第一封装还包括耦合到衬底层的底侧的管芯。 第二封装包括多排焊球，并且第二封装通过多排焊球附接到基板层的基本上平坦的表面。

公开(公告)号：WO2012067992A3

公开(公告)日：2012-12-20

申请号：PCT/US2011060553

申请日：2011-11-14

Applicant: TESSERA INC ,  HABA BELGACEM

Inventor： HABA BELGACEM

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L24/05 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/03001 ,  H01L2224/03003 ,  H01L2224/0311 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05576 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16145 ,  H01L2224/16221 ,  H01L2224/29018 ,  H01L2224/29026 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/20107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An assembly 100 and method of making same are provided. The assembly 100 can include a first component 105 including a dielectric region 120 having an exposed surface 122, a conductive pad 134 at the surface 122 defined by a conductive element 132 having at least a portion extending in an oscillating or spiral path along the surface 122, and a an electrically conductive bonding material 140 joined to the conductive pad 134 and bridging an exposed portion 137 of the dielectric surface 122 between adjacent segments 136, 138. The conductive pad 134 can permit electrical interconnection of the first component 105 with a second component 107 having a terminal 108 joined to the pad 134 through the electrically conductive bonding material 140. The path of the conductive element 132 may or may not overlap or cross itself.

Abstract translation: 提供组件100及其制造方法。 组件100可以包括第一部件105，其包括具有暴露表面122的电介质区域120，在由导电元件132限定的表面122处的导电焊盘134，导电元件132具有沿着表面122的振荡或螺旋路径延伸的至少一部分 以及连接到导电焊盘134并桥接相邻段136,138之间的电介质表面122的暴露部分137的导电接合材料140.导电焊盘134可以允许第一部件105与第二部件 107具有通过导电接合材料140接合到焊盘134的端子108.导电元件132的路径可以或可以不与其自身重叠或交叉。

公开(公告)号：WO2017087502A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/062247

申请日：2016-11-16

Applicant: INVENSAS CORPORATION

Inventor： KATKAR, Rajesh ,  PRABHU, Ashok, S. ,  VILLAVICENCIO, Grant ,  LEE, Sangil ,  ALATORRE, Roseann ,  DELACRUZ, Javier, A. ,  MCGRATH, Scott

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L23/49811 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/043 ,  H01L23/053 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15333 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

Abstract translation: 部件可以包括大致平面的元件，覆盖在大致平面元件上的增强介电层，覆盖增强介电层的封装以及多个引线键合。 每个引线键合可以在封装的主表面处具有尖端。 引线键合可具有在增强介电层内延伸的第一部分。 至少一些丝焊的第一部分可具有改变相应丝焊的延伸方向的弯曲。 增强介电层可以具有围绕相应的一些引线键合的突出区域，突出区域比相邻的突出区域之间的增强介电层的部分从通常平面元件的第一表面延伸到更大的峰值高度。 突出区域的峰高可以与增强介电层和单独引线键合之间的接触点重合。